公开(公告)号：US09823968B1

公开(公告)日：2017-11-21

申请号：US14832147

申请日：2015-08-21

Applicant: DATADIRECT NETWORKS, INC.

Inventor： Thomas E. Fugini ,  Michael J. Piszczek ,  William J Harker ,  Jason M. Cope ,  Pavan Kumar Uppu

IPC: G06F11/10 ,  G06F3/06

CPC classification number: G06F11/1076 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0689

Abstract: Variable Redundancy Distributed (VRD) RAID controller in a data storage environment contains embedded RAID logic permitting to choose and compute a desired redundancy coding scheme from a plurality thereof pre-programmed and embedded in a Compute Engine in the VRD RAID controller. “Write” or “Read” requests which are received from data generating entities, contain information identifying a type of the redundancy coding scheme of interest. The controller decodes the request, and automatically applies the desired computation to the incoming data without burdening the CPU with the computational activity. The variable redundancy computational ability of the subject systems provides an extremely versatile and flexible tool for RAID operations.

公开(公告)号：US08959420B1

公开(公告)日：2015-02-17

申请号：US13719750

申请日：2012-12-19

Applicant: DataDirect Networks, Inc.

Inventor： Michael J. Piszczek ,  Jason M. Cope ,  William J Harker ,  Pavan Kumar Uppu ,  Thomas E. Fugini

IPC: G06F11/00 ,  H03M13/00 ,  G06F12/02 ,  H03M13/05

CPC classification number: G06F12/10 ,  G06F11/1096 ,  Y02D10/13

Abstract: The present data storage system employs a memory controller with embedded logic to selectively XOR incoming data with data written in the memory to generate XOR parity data. The memory controller automatically performs XOR operations on incoming data based upon the address range associated with the memory “write” request. The system provides data migration and parity generation in a simple and effective manner and attains reduction in cost and power consumption. The memory controller may be built on the basis of FPGAs, thus providing an economical and miniature system.

Abstract translation: 本数据存储系统采用具有嵌入逻辑的存储器控​​制器来选择性地将输入数据输入到存储器中的数据，以产生XOR奇偶校验数据。 存储器控制器根据与存储器“写入”请求相关联的地址范围自动对输入数据执行异或操作。 该系统以简单有效的方式提供数据迁移和奇偶校验生成，并降低成本和功耗。 存储器控制器可以基于FPGA构建，从而提供经济和微型系统。