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1.发明申请公开(公告)号：US20170271864A1
公开(公告)日：2017-09-21
申请号：US15608898
申请日：2017-05-30
Applicant: DAVIDE ANDREA
Inventor： DAVIDE ANDREA
CPC classification number: H02H9/002 , H02J7/0018 , Y02T10/7055
Abstract: Disclosed is a battery and load equalization circuit that prevents the in-rush of current when batteries and/or loads are initially connected in parallel. Various techniques are used including charging, discharging and use of DC to DC converters to equalize charges between batteries and between batteries and capacitive loads.
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2.发明申请公开(公告)号：US20170271863A1
公开(公告)日：2017-09-21
申请号：US15608890
申请日：2017-05-30
Applicant: DAVIDE ANDREA
Inventor： DAVIDE ANDREA
CPC classification number: H02H9/002 , H02J7/0018 , Y02T10/7055
Abstract: Disclosed is a battery and load equalization circuit that prevents the in-rush of current when batteries and/or loads are initially connected in parallel. Various techniques are used including charging, discharging and use of DC to DC converters to equalize charges between batteries and between batteries and capacitive loads.
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