公开(公告)号：US20240304268A1

公开(公告)日：2024-09-12

申请号：US18540879

申请日：2023-12-15

Applicant: Faraday Technology Corp.

Inventor： Chih-Hung Wu ,  Ko-Ching Chao ,  Po-Wen Hsiao ,  Zhou-Lun Liou

IPC: G11C29/02 ,  G11C7/14 ,  G11C8/18

CPC classification number: G11C29/028 ,  G11C7/14 ,  G11C8/18

Abstract: A method and apparatus for performing self-calibration of receiver offset without shorting differential input terminals of a receiver are provided. The self-calibration includes: inputting input signals carrying predetermined data patterns into a plurality of receivers; performing data eye width measurement on the input signals received by the plurality of receivers to obtain multiple first data eye widths and multiple second data eye widths respectively corresponding to first and second data bytes; performing first offset calibration to make the multiple first data eye widths converge to a first common data eye width; performing second offset calibration to make the multiple second data eye widths be equal to the multiple first data eye widths, respectively, and converge to the first common data eye width; and performing reference voltage calibration on a reference voltage to optimize the multiple first data eye widths and the multiple second data eye widths.

公开(公告)号：US20170097654A1

公开(公告)日：2017-04-06

申请号：US15046425

申请日：2016-02-17

Applicant: Faraday Technology Corp.

Inventor： Chih-Hung Wu

IPC: G06F1/06 ,  G06F3/06

CPC classification number: G06F1/06 ,  G06F3/0611 ,  G06F3/0653 ,  G06F3/0673

Abstract: A Double Data Rate (DDR) gating method is applied to a memory controller of an associated DDR gating apparatus. The DDR gating method includes: outputting from the memory controller an outward clock signal to a memory, and receiving from the memory a backward clock signal corresponding to the outward clock signal, wherein the backward clock signal is utilized as reference for a data read operation of the memory controller with respect to the memory; and providing an input stage of the memory controller with a reference signal to generate, through single ended receiving of the input stage, gating-related information for performing gating when sampling the backward clock signal, and lengthening time of a preamble of the backward clock signal with aid of the single ended receiving of the input stage, for increasing a detection margin of the preamble.

公开(公告)号：US20230231560A1

公开(公告)日：2023-07-20

申请号：US17974532

申请日：2022-10-27

Applicant: Faraday Technology Corp.

Inventor： Ko-Ching Chao ,  Chih-Hung Wu ,  Po-Wen Hsiao ,  Zhou-Lun Liou

IPC: H03L7/00 ,  H03K19/21 ,  H03K21/02 ,  G11C11/4076

CPC classification number: H03L7/00 ,  H03K19/21 ,  H03K21/023 ,  G11C11/4076

Abstract: A method for performing divided-clock phase synchronization in a multi-divided-clock system, an associated synchronization control circuit, an associated synchronization control sub-circuit and an associated electronic device are provided. The method may include: performing frequency division operations according to a source clock to generate a first divided clock and a second divided clock; performing phase relationship detection on the first divided clock according to the second divided clock to generate a phase relationship detection result signal; performing a logic operation on a first phase selection result output signal and the phase relationship detection result signal to generate a second phase selection result output signal; and outputting one of the second divided clock and an inverted signal of the second divided clock according to the second phase selection result output signal, for further use in a physical layer circuit.

公开(公告)号：US09946294B2

公开(公告)日：2018-04-17

申请号：US15046425

申请日：2016-02-17

Applicant: Faraday Technology Corp.

Inventor： Chih-Hung Wu

IPC: G11C8/00 ,  G06F1/06 ,  G06F3/06

CPC classification number: G06F1/06 ,  G06F3/0611 ,  G06F3/0653 ,  G06F3/0673

Abstract: A Double Data Rate (DDR) gating method is applied to a memory controller of an associated DDR gating apparatus. The DDR gating method includes: outputting from the memory controller an outward clock signal to a memory, and receiving from the memory a backward clock signal corresponding to the outward clock signal, wherein the backward clock signal is utilized as reference for a data read operation of the memory controller with respect to the memory; and providing an input stage of the memory controller with a reference signal to generate, through single ended receiving of the input stage, gating-related information for performing gating when sampling the backward clock signal, and lengthening time of a preamble of the backward clock signal with aid of the single ended receiving of the input stage, for increasing a detection margin of the preamble.

公开(公告)号：US11736108B2

公开(公告)日：2023-08-22

申请号：US17974532

申请日：2022-10-27

Applicant: Faraday Technology Corp.

Inventor： Ko-Ching Chao ,  Chih-Hung Wu ,  Po-Wen Hsiao ,  Zhou-Lun Liou

IPC: H03L7/00 ,  G11C11/4076 ,  H03K21/02 ,  H03K19/21

CPC classification number: H03L7/00 ,  G11C11/4076 ,  H03K19/21 ,  H03K21/023

Abstract: A method for performing divided-clock phase synchronization in a multi-divided-clock system, an associated synchronization control circuit, an associated synchronization control sub-circuit and an associated electronic device are provided. The method may include: performing frequency division operations according to a source clock to generate a first divided clock and a second divided clock; performing phase relationship detection on the first divided clock according to the second divided clock to generate a phase relationship detection result signal; performing a logic operation on a first phase selection result output signal and the phase relationship detection result signal to generate a second phase selection result output signal; and outputting one of the second divided clock and an inverted signal of the second divided clock according to the second phase selection result output signal, for further use in a physical layer circuit.