公开(公告)号：US09257530B1

公开(公告)日：2016-02-09

申请号：US14471660

申请日：2014-08-28

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Gerd Zschatzsch ,  Stefan Flachowsky ,  Jan Hoentschel

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/283

CPC classification number: H01L29/66545 ,  H01L21/283 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76885 ,  H01L23/485 ,  H01L29/517 ,  H01L29/66606 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One exemplary embodiment provides a method of making an integrated circuit. The method includes forming a dummy gate structure above a semiconductor substrate, etching an exposed semiconductor substrate outside the dummy gate structure, depositing silicon oxide over the dummy gate structure and the semiconductor substrate to form a silicon oxide layer, etching source and drain contact vias through the silicon oxide layer, implanting source and drain dopants through the source and drain contact vias, removing the dummy gate structure, forming a final gate structure, etching substantially all of the silicon oxide layer, and depositing an ultra low K dielectric to form an ultra low K dielectric layer.

Abstract translation: 一个示例性实施例提供了制造集成电路的方法。 该方法包括在半导体衬底之上形成虚拟栅极结构，蚀刻在虚拟栅极结构之外的暴露的半导体衬底，在虚拟栅极结构和半导体衬底上沉积氧化硅以形成氧化硅层，蚀刻源极和漏极接触通孔 氧化硅层，通过源极和漏极接触通孔注入源极和漏极掺杂剂，去除虚拟栅极结构，形成最终的栅极结构，蚀刻基本上所有的氧化硅层，以及沉积超低K电介质以形成超 低K电介质层。

公开(公告)号：US20160064513A1

公开(公告)日：2016-03-03

申请号：US14471736

申请日：2014-08-28

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ralf Richter ,  Gerd Zschatzsch ,  Joanna Wasyluk

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L21/762 ,  H01L21/324

CPC classification number: H01L29/0657 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/2636 ,  H01L21/3247 ,  H01L21/76224 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66651 ,  H01L29/78

Abstract: Integrated circuits and methods for manufacturing the same are provided. A method for manufacturing an integrated circuit includes forming a first and second STI insulator in a substrate, and bowing a substrate surface between the first and second STI insulators. A transistor is formed between the first and second STI insulators.

Abstract translation: 提供了集成电路及其制造方法。 一种用于制造集成电路的方法包括在衬底中形成第一和第二STI绝缘体，并且在第一和第二STI绝缘体之间弯曲衬底表面。 在第一和第二STI绝缘体之间形成晶体管。

公开(公告)号：US20160064515A1

公开(公告)日：2016-03-03

申请号：US14471660

申请日：2014-08-28

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Gerd Zschatzsch ,  Stefan Flachowsky ,  Jan Hoentschel

IPC: H01L29/66 ,  H01L21/283

CPC classification number: H01L29/66545 ,  H01L21/283 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76885 ,  H01L23/485 ,  H01L29/517 ,  H01L29/66606 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One exemplary embodiment provides a method of making an integrated circuit. The method includes forming a dummy gate structure above a semiconductor substrate, etching an exposed semiconductor substrate outside the dummy gate structure, depositing silicon oxide over the dummy gate structure and the semiconductor substrate to form a silicon oxide layer, etching source and drain contact vias through the silicon oxide layer, implanting source and drain dopants through the source and drain contact vias, removing the dummy gate structure, forming a final gate structure, etching substantially all of the silicon oxide layer, and depositing an ultra low K dielectric to form an ultra low K dielectric layer.

Abstract translation: 一个示例性实施例提供了制造集成电路的方法。 该方法包括在半导体衬底之上形成虚拟栅极结构，蚀刻在虚拟栅极结构之外的暴露的半导体衬底，在虚拟栅极结构和半导体衬底上沉积氧化硅以形成氧化硅层，蚀刻源极和漏极接触通孔 氧化硅层，通过源极和漏极接触通孔注入源极和漏极掺杂剂，去除虚拟栅极结构，形成最终的栅极结构，蚀刻基本上所有的氧化硅层，以及沉积超低K电介质以形成超 低K电介质层。