公开(公告)号：US09530864B2

公开(公告)日：2016-12-27

申请号：US14314404

申请日：2014-06-25

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Steven J. Bentley ,  Michael J. Hargrove ,  Chia-Yu Chen ,  Ryan O. Jung ,  Sivanandha K. Kanakasabapathy ,  Tenko Yamashita

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/6656 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7834 ,  H01L29/7836

Abstract: Approaches for providing junction overlap control in a semiconductor device are provided. Specifically, at least one approach includes: providing a gate over a substrate; forming a set of junction extensions in a channel region adjacent the gate; forming a set of spacer layers along each of a set of sidewalls of the gate; removing the gate between the set of spacer layers to form an opening; removing, from within the opening, an exposed sacrificial spacer layer of the set of spacer layers, the exposed sacrificial spacer layer defining a junction extension overlap linear distance from the set of sidewalls of the gate; and forming a replacement gate electrode within the opening. This results in a highly scaled advanced transistor having precisely defined junction profiles and well-controlled gate overlap geometry achieved using extremely abrupt junctions whose surface position is defined using the set of spacer layers.

Abstract translation: 提供了在半导体器件中提供接合重叠控制的方法。 具体地，至少一种方法包括：在衬底上提供栅极; 在与栅极相邻的沟道区域中形成一组结延伸部分; 沿着栅极的一组侧壁中的每一个形成一组间隔层; 移除所述一组间隔层之间的栅极以形成开口; 从所述开口内去除所述一组间隔层的暴露的牺牲间隔层，所述暴露的牺牲间隔层限定结延伸部与所述栅极侧壁的所述一组侧壁重叠线性距离; 以及在所述开口内形成替换栅电极。 这导致具有精确限定的接合轮廓的高度缩放的先进晶体管，并且使用极其突出的接头实现良好控制的栅极重叠几何，其表面位置使用该组间隔层限定。

公开(公告)号：US09368591B2

公开(公告)日：2016-06-14

申请号：US14334950

申请日：2014-07-18

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Steven J. Bentley ,  Ajey Poovannummoottil Jacob ,  Chia-Yu Chen ,  Tenko Yamashita

IPC: H01L21/338 ,  H01L29/45

CPC classification number: H01L29/495 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/02532 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/167 ,  H01L29/42376 ,  H01L29/45 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/78

Abstract: Embodiments of the present invention provide transistors with controlled junctions and methods of fabrication. A dummy spacer is used during the majority of front end of line (FEOL) processing. Towards the end of the FEOL processing, the dummy spacers are removed and replaced with a final spacer material. Embodiments of the present invention allow the use of a very low-k material, which is highly thermally-sensitive, by depositing it late in the flow. Additionally, the position of the gate with respect to the doped regions is highly controllable, while dopant diffusion is minimized through reduced thermal budgets. This allows the creation of extremely abrupt junctions whose surface position is defined using a sacrificial spacer. This spacer is then removed prior to final gate deposition, allowing a fixed gate overlap that is defined by the spacer thickness and any diffusion of the dopant species.

Abstract translation: 本发明的实施例提供具有受控结的晶体管和制造方法。 在大多数前端（FEOL）处理中使用虚拟间隔器。 在FEOL处理结束之后，去除虚拟间隔物并用最后的间隔物材料代替。 本发明的实施例允许使用非常低k的材料，其通过在流动中较晚沉积而具有高度热敏感性。 此外，栅极相对于掺杂区域的位置是高度可控的，而掺杂剂扩散通过减少的热预算被最小化。 这允许创建极其突出的接头，其表面位置使用牺牲隔离物限定。 然后在最终栅极沉积之前去除该间隔物，允许由间隔物厚度和掺杂剂物质的任何扩散限定的固定栅极重叠。

公开(公告)号：US20150380514A1

公开(公告)日：2015-12-31

申请号：US14314404

申请日：2014-06-25

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Steven J. Bentley ,  Michael J. Hargrove ,  Chia-Yu Chen ,  Ryan O. Jung ,  Sivanandha K. Kanakasabapathy ,  Tenko Yamashita

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/6656 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7834 ,  H01L29/7836

Abstract: Approaches for providing junction overlap control in a semiconductor device are provided. Specifically, at least one approach includes: providing a gate over a substrate; forming a set of junction extensions in a channel region adjacent the gate; forming a set of spacer layers along each of a set of sidewalls of the gate; removing the gate between the set of spacer layers to form an opening; removing, from within the opening, an exposed sacrificial spacer layer of the set of spacer layers, the exposed sacrificial spacer layer defining a junction extension overlap linear distance from the set of sidewalls of the gate; and forming a replacement gate electrode within the opening. This results in a highly scaled advanced transistor having precisely defined junction profiles and well-controlled gate overlap geometry achieved using extremely abrupt junctions whose surface position is defined using the set of spacer layers.

Abstract translation: 提供了在半导体器件中提供接合重叠控制的方法。 具体地，至少一种方法包括：在衬底上提供栅极; 在与栅极相邻的沟道区域中形成一组结延伸部分; 沿着栅极的一组侧壁中的每一个形成一组间隔层; 移除所述一组间隔层之间的栅极以形成开口; 从所述开口内去除所述一组间隔层的暴露的牺牲间隔层，所述暴露的牺牲间隔层限定结延伸部与所述栅极侧壁的所述一组侧壁重叠线性距离; 以及在所述开口内形成替换栅电极。 这导致具有精确限定的接合轮廓的高度缩放的先进晶体管，并且使用极其突出的接头实现良好控制的栅极重叠几何，其表面位置使用该组间隔层限定。

公开(公告)号：US20160254361A1

公开(公告)日：2016-09-01

申请号：US15154495

申请日：2016-05-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Steven J. Bentley ,  Ajey Poovannummoottil Jacob ,  Chia-Yu Chen ,  Tenko Yamashita

IPC: H01L29/49 ,  H01L29/10 ,  H01L29/423 ,  H01L21/02 ,  H01L29/45 ,  H01L29/167 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/51

CPC classification number: H01L29/495 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/02532 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/167 ,  H01L29/42376 ,  H01L29/45 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/78

Abstract: Embodiments of the present invention provide transistors with controlled junctions and methods of fabrication. A dummy spacer is used during the majority of front end of line (FEOL) processing. Towards the end of the FEOL processing, the dummy spacers are removed and replaced with a final spacer material. Embodiments of the present invention allow the use of a very low-k material, which is highly thermally-sensitive, by depositing it late in the flow. Additionally, the position of the gate with respect to the doped regions is highly controllable, while dopant diffusion is minimized through reduced thermal budgets. This allows the creation of extremely abrupt junctions whose surface position is defined using a sacrificial spacer. This spacer is then removed prior to final gate deposition, allowing a fixed gate overlap that is defined by the spacer thickness and any diffusion of the dopant species.

Abstract translation: 本发明的实施例提供具有受控结的晶体管和制造方法。 在大多数前端（FEOL）处理中使用虚拟间隔器。 在FEOL处理结束之后，去除虚拟间隔物并用最后的间隔物材料代替。 本发明的实施例允许使用非常低k的材料，其通过在流动中较晚沉积而具有高度热敏感性。 此外，栅极相对于掺杂区域的位置是高度可控的，而掺杂剂扩散通过减少的热预算被最小化。 这允许创建极其突出的接头，其表面位置使用牺牲隔离物限定。 然后在最终栅极沉积之前去除该间隔物，允许由间隔物厚度和掺杂剂物质的任何扩散限定的固定栅极重叠。

公开(公告)号：US20160020335A1

公开(公告)日：2016-01-21

申请号：US14334950

申请日：2014-07-18

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Steven J. Bentley ,  Ajey Poovannummoottil Jacob ,  Chia-Yu Chen ,  Tenko Yamashita

IPC: H01L29/808 ,  H01L29/45 ,  H01L29/66

CPC classification number: H01L29/495 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/02532 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/167 ,  H01L29/42376 ,  H01L29/45 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/78

Abstract: Embodiments of the present invention provide transistors with controlled junctions and methods of fabrication. A dummy spacer is used during the majority of front end of line (FEOL) processing. Towards the end of the FEOL processing, the dummy spacers are removed and replaced with a final spacer material. Embodiments of the present invention allow the use of a very low-k material, which is highly thermally-sensitive, by depositing it late in the flow. Additionally, the position of the gate with respect to the doped regions is highly controllable, while dopant diffusion is minimized through reduced thermal budgets. This allows the creation of extremely abrupt junctions whose surface position is defined using a sacrificial spacer. This spacer is then removed prior to final gate deposition, allowing a fixed gate overlap that is defined by the spacer thickness and any diffusion of the dopant species.

Abstract translation: 本发明的实施例提供具有受控结的晶体管和制造方法。 在大多数前端（FEOL）处理中使用虚拟间隔器。 在FEOL处理结束之后，去除虚拟间隔物并用最后的间隔物材料代替。 本发明的实施例允许使用非常低k的材料，其通过在流动中较晚沉积而具有高度热敏感性。 此外，栅极相对于掺杂区域的位置是高度可控的，而掺杂剂扩散通过减少的热预算被最小化。 这允许创建极其突出的接头，其表面位置使用牺牲隔离物限定。 然后在最终栅极沉积之前去除该间隔物，允许由间隔物厚度和掺杂剂物质的任何扩散限定的固定栅极重叠。