公开(公告)号：US09390928B2

公开(公告)日：2016-07-12

申请号：US14059842

申请日：2013-10-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Emre Alptekin ,  Hari V. Mallela ,  Reinaldo Vega

IPC: H01L21/28 ,  H01L29/772 ,  H01L29/66 ,  H01L29/49 ,  H01L29/51 ,  H01L27/088 ,  H01L27/12 ,  H01L21/8234 ,  H01L21/84

CPC classification number: H01L21/28008 ,  H01L21/823468 ,  H01L21/84 ,  H01L27/088 ,  H01L27/1203 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/772

Abstract: Capacitive coupling between a gate electrode and underlying portions of the source and drain regions can be enhanced while suppressing capacitive coupling between the gate electrode and laterally spaced elements such as contact via structures for the source and drain regions. A transistor including a gate electrode and source and drain regions is formed employing a disposable gate spacer. The disposable gate spacer is removed to form a spacer cavity, which is filled with an anisotropic dielectric material to form an anisotropic gate spacer. The anisotropic dielectric material is aligned with an electrical field such that lengthwise directions of the molecules of the anisotropic dielectric material are aligned vertically within the spacer cavity. The anisotropic gate spacer provides a higher dielectric constant along the vertical direction and a lower dielectric constant along the horizontal direction.

Abstract translation: 可以增强栅极电极和源极和漏极区域的下部之间的电容耦合，同时抑制栅极电极和横向间隔开的元件之间的电容耦合，例如用于源极和漏极区域的接触通孔结构。 使用一次性栅极间隔物形成包括栅极和源极和漏极区的晶体管。 去除一次性栅极间隔物以形成间隔腔，其填充有各向异性介电材料以形成各向异性栅极间隔物。 各向异性介电材料与电场对准，使得各向异性介电材料的分子的纵向方向在间隔空腔内垂直排列。 各向异性栅极间隔沿垂直方向提供较高介电常数，沿水平方向提供较低介电常数。

公开(公告)号：US09337334B2

公开(公告)日：2016-05-10

申请号：US14257395

申请日：2014-04-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hari V. Mallela ,  Edward J. Nowak ,  Yunsheng Song ,  Reinaldo A. Vega ,  Keith Kwong Hon Wong ,  Zhijian Yang

IPC: H01L21/02 ,  H01L29/78 ,  H01L29/49 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L21/28 ,  H03K17/687 ,  H01L29/51

CPC classification number: H01L29/78391 ,  H01L21/28026 ,  H01L21/28291 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/49 ,  H01L29/516 ,  H01L29/66568 ,  H01L29/6684 ,  H03K17/687

Abstract: A semiconductor memory device including a channel region and a ferromagnetic gate is provided. The channel region can be formed within a semiconductor nanowire. The ferromagnetic gate is programmed with a selected orientation of magnetization by the electrical current that passes through the channel region in one direction or another. The orientation of the magnetization in the ferromagnetic gate can be detected by changes in the threshold voltage of a field effect transistor employing the ferromagnetic gate as a gate electrode, or can be detected by the resistance of the channel region that changes with the orientation of the magnetization in a two terminal device.

Abstract translation: 提供了包括沟道区和铁磁栅的半导体存储器件。 沟道区可以形成在半导体纳米线内。 铁磁栅极通过在一个方向上通过沟道区域的电流以选定的磁化取向来编程。 可以通过使用铁磁栅极作为栅电极的场效应晶体管的阈值电压的变化来检测铁磁栅极中的磁化方向，或者可以通过随着取向的变化而改变的沟道区域的电阻来检测 二端装置的磁化。