公开(公告)号：US10242946B2

公开(公告)日：2019-03-26

申请号：US15418001

申请日：2017-01-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Irene Y. L. Lin ,  Lei Yuan ,  Mahbub Rashed

IPC: G06F17/50 ,  H01L27/02 ,  H01L23/522 ,  H01L23/528 ,  H01L27/118

Abstract: A multi-layer integrated circuit structure includes (among other components) a first layer having gate conductors, a second layer having M0 conductors, a third layer having M1 conductors, and a fourth layer having M2 conductors. The M0 and M2 conductors are perpendicular to the gate conductors, and parallel to each other. The M1 conductors connect the M0 conductors to the M2 conductors. The gate conductors are positioned in the first layer in the same locations in the horizontal direction. The M1 conductors are positioned in the third layer in a different location in the horizontal direction that is different from the locations of the gate conductors, so that the M1 conductors do not overlap any of the gate conductors, solving a substantial routing challenge for the input and output contacts.

公开(公告)号：US20180218981A1

公开(公告)日：2018-08-02

申请号：US15418001

申请日：2017-01-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Irene Y. L. Lin ,  Lei Yuan ,  Mahbub Rashed

IPC: H01L23/528 ,  H01L23/522 ,  H01L27/02 ,  H01L27/118 ,  G06F17/50

CPC classification number: H01L23/5286 ,  G06F17/5077 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2027/11875 ,  H01L2027/11887

Abstract: A multi-layer integrated circuit structure includes (among other components) a first layer having gate conductors, a second layer having M0 conductors, a third layer having M1 conductors, and a fourth layer having M2 conductors. The M0 and M2 conductors are perpendicular to the gate conductors, and parallel to each other. The M1 conductors connect the M0 conductors to the M2 conductors. The gate conductors are positioned in the first layer in the same locations in the horizontal direction. The M1 conductors are positioned in the third layer in a different location in the horizontal direction that is different from the locations of the gate conductors, so that the M1 conductors do not overlap any of the gate conductors, solving a substantial routing challenge for the input and output contacts.