公开(公告)号：US20190267946A1

公开(公告)日：2019-08-29

申请号：US16367113

申请日：2019-03-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shafiullah Syed ,  Abdellatif Bellaouar ,  Chi Zhang

IPC: H03F1/02 ,  H03F3/195 ,  H04B1/04 ,  H03F3/217

Abstract: An apparatus, comprising an input transformer; a first differential transistor pair configured to receive a first back gate bias voltage; a second differential transistor pair configured to receive a second back gate bias voltage; a cross-coupled neutralization cap comprising PMOS or NMOS transistors and configured to receive a third back gate bias voltage; and an output transformer. A method of fixing at least one back gate bias voltage to impart a desired capacitance to the transistors of at least one of the first differential transistor pair, the second differential transistor pair, or the neutralization cap. The apparatus and method may provide a power amplifier having improved linearity and efficiency.

公开(公告)号：US10680557B2

公开(公告)日：2020-06-09

申请号：US16367113

申请日：2019-03-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shafiullah Syed ,  Abdellatif Bellaouar ,  Chi Zhang

IPC: H03F1/02 ,  H03F3/195 ,  H04B1/04 ,  H03F3/45 ,  H03F3/217 ,  H03F1/14 ,  H01L21/84 ,  H01L27/12

Abstract: An apparatus, comprising an input transformer; a first differential transistor pair configured to receive a first back gate bias voltage; a second differential transistor pair configured to receive a second back gate bias voltage; a cross-coupled neutralization cap comprising PMOS or NMOS transistors and configured to receive a third back gate bias voltage; and an output transformer. A method of fixing at least one back gate bias voltage to impart a desired capacitance to the transistors of at least one of the first differential transistor pair, the second differential transistor pair, or the neutralization cap. The apparatus and method may provide a power amplifier having improved linearity and efficiency.

公开(公告)号：US10291183B1

公开(公告)日：2019-05-14

申请号：US15908678

申请日：2018-02-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shafiullah Syed ,  Abdellatif Bellaouar ,  Chi Zhang

IPC: H03F1/02 ,  H03F3/195 ,  H03F3/21 ,  H03F3/45 ,  H03F1/22 ,  H04B1/04 ,  H03F3/217 ,  H01L21/84 ,  H01L27/12

Abstract: An apparatus, comprising an input transformer; a first differential transistor pair configured to receive a first back gate bias voltage; a second differential transistor pair configured to receive a second back gate bias voltage; a cross-coupled neutralization cap comprising PMOS or NMOS transistors and configured to receive a third back gate bias voltage; and an output transformer. A method of fixing at least one back gate bias voltage to impart a desired capacitance to the transistors of at least one of the first differential transistor pair, the second differential transistor pair, or the neutralization cap. The apparatus and method may provide a power amplifier having improved linearity and efficiency.