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公开(公告)号：US20200036363A1
公开(公告)日：2020-01-30
申请号：US16591144
申请日：2019-10-02
Applicant: GLOBALFOUNDRIES INC.
Inventor： Vincent J. McGahay , Bhupesh Chandra
Abstract: The present disclosure relates to semiconductor structures and, more particularly, to artificially oriented piezoelectric films for integrated filters and methods of manufacture. The structure includes: a piezoelectric film with effective crystalline orientations of the polar axis rotated 90 degrees from a natural orientation for planar deposited films; and a conductor pattern formed on a surface of the piezoelectric film.
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公开(公告)号：US09443776B2
公开(公告)日：2016-09-13
申请号：US14729446
申请日：2015-06-03
Applicant: GLOBALFOUNDRIES INC.
Inventor： Ronald G. Filippi , Jason P. Gill , Vincent J. McGahay , Paul S. McLaughlin , Conal E. Murray , Hazara S. Rathore , Thomas M. Shaw , Ping-Chuan Wang
IPC: H01L23/00 , H01L21/66 , H01L23/522 , H05K1/09 , H05K1/02
CPC classification number: H01L22/34 , H01L22/32 , H01L23/5226 , H01L23/562 , H01L2924/0002 , H05K1/0268 , H05K1/0269 , H05K1/092 , Y10S438/927 , Y10T29/49004 , H01L2924/00
Abstract: A test structure used to determine reliability performance includes a patterned metallization structure having multiple interfaces, which provide stress risers. A dielectric material surrounds the metallization structure, where a mismatch in coefficients of thermal expansion (CTE) between the metallization structure and the surrounding dielectric material exist such that a thermal strain value is provided to cause failures under given stress conditions as a result of CTE mismatch to provide a yield indicative of reliability for a manufacturing design.
Abstract translation: 用于确定可靠性性能的测试结构包括具有多个界面的图案化金属化结构，其提供应力梯度。 电介质材料围绕金属化结构，其中存在金属化结构和周围电介质材料之间的热膨胀系数（CTE）不匹配，使得提供热应变值以引起由于CTE失配导致的给定应力条件下的故障 以提供指示制造设计的可靠性的产量。
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公开(公告)号：US10546822B2
公开(公告)日：2020-01-28
申请号：US15690398
申请日：2017-08-30
Applicant: GLOBALFOUNDRIES INC.
Inventor： Nicholas A. Polomoff , Vincent J. McGahay
IPC: H01L21/70 , H01L23/58 , H01L21/768 , H01L23/00
Abstract: A seal ring structure of an integrated circuit including a first discontinuous seal wall circumscribing a first portion of the integrated circuit, the first seal wall forming a first pattern on a substrate, and a second discontinuous seal wall circumscribing a second portion of the integrated circuit, the second seal wall forming a second pattern on the substrate and the second portion being at least partially offset from the first portion, wherein the first pattern of the first seal wall interlocks with the second pattern of the second seal wall such that the patterns are interweaved without intersecting, wherein a space is formed between the seal walls, the space creating a non-linear path to the integrated circuit, and wherein the seal ring structure fully circumscribes the integrated circuit. A method of forming such a seal ring structure is also disclosed.
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公开(公告)号：US20180375494A1
公开(公告)日：2018-12-27
申请号：US15634397
申请日：2017-06-27
Applicant: GLOBALFOUNDRIES INC.
Inventor： Vincent J. McGahay , Bhupesh Chandra
IPC: H03H9/56 , H01L41/18 , H01L41/257
CPC classification number: H03H9/56 , H01L41/18 , H01L41/257 , H03H3/02 , H03H3/08 , H03H9/02015 , H03H9/02543
Abstract: The present disclosure relates to semiconductor structures and, more particularly, to artificially oriented piezoelectric films for integrated filters and methods of manufacture. The structure includes: a piezoelectric film with effective crystalline orientations of the polar axis rotated 90 degrees from a natural orientation for planar deposited films; and a conductor pattern formed on a surface of the piezoelectric film.
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公开(公告)号：US10109600B1
公开(公告)日：2018-10-23
申请号：US15702316
申请日：2017-09-12
Applicant: GLOBALFOUNDRIES INC.
Inventor： Vincent J. McGahay , Nicholas A. Polomoff
IPC: H01L23/48 , H01L23/00 , H01L23/66 , H01L21/3105 , H01L21/311 , H01L21/768
Abstract: The present disclosure relates to semiconductor structures and, more particularly, to continuous crackstop structures and methods of manufacture. The structure includes a continuous crackstop having a wall which switches back (switchbacks) on itself multiple times to form an enclosure about an active area of a chip.
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Patent Agency Ranking
公开(公告)号：US10062748B1
公开(公告)日：2018-08-28
申请号：US15443276
申请日：2017-02-27
Applicant: GLOBALFOUNDRIES INC.
Inventor： Anthony K. Stamper , Vincent J. McGahay , Zhong-Xiang He
IPC: H01L23/48 , H01L29/06 , H01L23/31 , H01L23/528
Abstract: The present disclosure relates to semiconductor structures and, more particularly, to segmented guard-ring and chip edge seals and methods of manufacture. The structure includes: a guard ring structure formed in a low-k dielectric material; and an edge seal structure formed through the low-k dielectric material to at least a substrate underneath the low-k dielectric material.
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公开(公告)号：US10438902B2
公开(公告)日：2019-10-08
申请号：US15698027
申请日：2017-09-07
Applicant: GLOBALFOUNDRIES INC.
Inventor： Vincent J. McGahay , Nicholas A. Polomoff , Shaoning Yao , Anupam Arora
Abstract: The present disclosure relates to semiconductor structures and, more particularly, to arc resistant crackstop structures and methods of manufacture. The structure includes: a crackstop structure comprising dual rails surrounding an active area of an integrated circuit; and a through-BOx electrical contact electrically connecting each of the dual rails to an underlying substrate.
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公开(公告)号：US09362230B1
公开(公告)日：2016-06-07
申请号：US14722302
申请日：2015-05-27
Applicant: GLOBALFOUNDRIES INC.
Inventor： Lawrence A. Clevenger , Vincent J. McGahay , Joyeeta Nag , Yiheng Xu
IPC: H01L21/265 , H01L23/532 , H01L21/285 , H01L21/3213 , H01L21/768 , H01L23/528
CPC classification number: H01L21/76892 , H01L21/28556 , H01L21/28562 , H01L21/3105 , H01L21/76825 , H01L21/76885 , H01L23/5256 , H01L28/24 , H01L2924/0002 , H01L2924/00
Abstract: Electrically conductive structures and methods of making electrically conductive structures. The methods include providing a dielectric layer of a material having a top surface and a dielectric constant of less than 3; rastering a gas cluster ion beam to form a patterned modified surface region of the top surface of the dielectric layer; and selectively forming an electrically conductive thin film on the patterned modified surface region using atomic layer deposition.
Abstract translation: 导电结构和制造导电结构的方法。 所述方法包括提供具有上表面和介电常数小于3的材料的电介质层; 清理气体簇离子束以形成电介质层的顶表面的图案化的改性表面区域; 并使用原子层沉积在图案化的改性表面区域上选择性地形成导电薄膜。
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公开(公告)号：US10483943B2
公开(公告)日：2019-11-19
申请号：US15634397
申请日：2017-06-27
Applicant: GLOBALFOUNDRIES INC.
Inventor： Vincent J. McGahay , Bhupesh Chandra
Abstract: The present disclosure relates to semiconductor structures and, more particularly, to artificially oriented piezoelectric films for integrated filters and methods of manufacture. The structure includes: a piezoelectric film with effective crystalline orientations of the polar axis rotated 90 degrees from a natural orientation for planar deposited films; and a conductor pattern formed on a surface of the piezoelectric film.
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公开(公告)号：US20190067210A1
公开(公告)日：2019-02-28
申请号：US15690398
申请日：2017-08-30
Applicant: GLOBALFOUNDRIES INC.
Inventor： Nicholas A. Polomoff , Vincent J. McGahay
Abstract: A seal ring structure of an integrated circuit including a first discontinuous seal wall circumscribing a first portion of the integrated circuit, the first seal wall forming a first pattern on a substrate, and a second discontinuous seal wall circumscribing a second portion of the integrated circuit, the second seal wall forming a second pattern on the substrate and the second portion being at least partially offset from the first portion, wherein the first pattern of the first seal wall interlocks with the second pattern of the second seal wall such that the patterns are interweaved without intersecting, wherein a space is formed between the seal walls, the space creating a non-linear path to the integrated circuit, and wherein the seal ring structure fully circumscribes the integrated circuit. A method of forming such a seal ring structure is also disclosed.
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