公开(公告)号：US10818803B1

公开(公告)日：2020-10-27

申请号：US16516623

申请日：2019-07-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Julien Frougier ,  Ali Razavieh

IPC: H01L21/00 ,  H01L27/00 ,  H01L29/00 ,  H01L29/786 ,  H01L29/10 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/16

Abstract: Structures for a field-effect transistor and methods of forming structures for a field-effect transistor. A source/drain region is connected with a channel layer, and a gate structure extends across the channel layer. The channel layer is composed of a two-dimensional material.

公开(公告)号：US10236292B1

公开(公告)日：2019-03-19

申请号：US16156082

申请日：2018-10-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Julien Frougier ,  Ruilong Xie ,  Puneet H. Suvarna ,  Hiroaki Niimi ,  Steven J. Bentley ,  Ali Razavieh

IPC: H01L21/02 ,  H01L29/66 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/285 ,  H01L21/768 ,  H01L29/45 ,  H01L29/786

Abstract: The present disclosure relates generally to wrap around contact formation in source/drain regions of a semiconductor device such as an integrated circuit (IC), and more particularly, to stacked IC structures containing complementary FETs (CFETs) having wrap around contacts and methods of forming the same. Disclosed is a stacked IC structure including a first FET on a substrate, a second FET vertically stacked above the first FET, a dielectric layer above the second FET, and a spacer layer between FETs, wherein each FET has an electrically isolated wrap-around contact formed therearound.

公开(公告)号：US09991352B1

公开(公告)日：2018-06-05

申请号：US15651282

申请日：2017-07-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Julien Frougier ,  Ali Razavieh ,  Ruilong Xie ,  Steven Bentley

IPC: H01L29/76 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/42364 ,  H01L29/0665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785

Abstract: A method that includes forming a patterned stack of materials comprising at least one channel semiconductor material layer and first and second layers of sacrificial material positioned above and below, respectively, the at least one channel semiconductor material layer, forming a replacement gate cavity above the patterned stack of materials and performing an etching process through the gate cavity to selectively remove at least a portion of the first and second layers of sacrificial material relative to the at least one channel semiconductor material layer. The method further includes performing a second etching process to form a reduced-thickness portion of the channel semiconductor material layer that has a final thickness that is less than the initial thickness and forming a replacement gate structure around at least the reduced-thickness portion of the channel semiconductor material layer.

公开(公告)号：US10192867B1

公开(公告)日：2019-01-29

申请号：US15888401

申请日：2018-02-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Julien Frougier ,  Ruilong Xie ,  Puneet H. Suvarna ,  Hiroaki Niimi ,  Steven J. Bentley ,  Ali Razavieh

IPC: H01L21/02 ,  H01L29/66 ,  H01L27/092 ,  H01L29/786 ,  H01L29/45 ,  H01L21/8238 ,  H01L21/768 ,  H01L21/285

Abstract: The present disclosure relates generally to wrap around contact formation in source/drain regions of a semiconductor device such as an integrated circuit (IC), and more particularly, to stacked IC structures containing complementary FETs (CFETs) having wrap around contacts and methods of forming the same. Disclosed is a stacked IC structure including a first FET on a substrate, a second FET vertically stacked above the first FET, a dielectric layer above the second FET, and a spacer layer between FETs, wherein each FET has an electrically isolated wrap-around contact formed therearound.