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    Gate silicidation
    2.
    发明授权
    Gate silicidation 有权
    栅极硅化

    公开(公告)号：US08906794B1

    公开(公告)日：2014-12-09

    申请号：US13956844

    申请日：2013-08-01

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Joachim Patzer ,  Ardechir Pakfar ,  Clemens Fitz ,  Dominic Thurmer

    IPC: H01L21/00 ,  H01L27/088 ,  H01L21/28

    CPC classification number: H01L21/823443 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/32053 ,  H01L21/321 ,  H01L21/324 ,  H01L27/0629 ,  H01L27/088 ,  H01L29/4925 ,  H01L29/4933

    Abstract: A method for performing silicidation of gate electrodes includes providing a semiconductor device having first and second transistors with first and second gate electrodes formed on a semiconductor substrate, forming an oxide layer on the first and second gate electrodes and the semiconductor substrate, forming a cover layer on the oxide layer, and back etching the cover layer to expose portions of the oxide layer above the first and second gate electrodes while maintaining a portion of the cover layer between the first and second gate electrodes. Furthermore, the exposed portions of the oxide layer are removed from the first and second gate electrodes to expose upper portions of the first and second gate electrodes, while maintaining a portion of the oxide layer between the first and second gate electrodes, and a silicidation of the exposed upper portions of the first and second gate electrodes is performed.

    Abstract translation: 一种用于执行栅电极的硅化的方法包括提供具有第一和第二晶体管的半导体器件，其中第一和第二栅电极形成在半导体衬底上，在第一和第二栅电极和半导体衬底上形成氧化物层，形成覆盖层 在所述氧化物层上，并且背面蚀刻所述覆盖层以暴露所述第一和第二栅电极之上的所述氧化物层的部分，同时保持所述覆盖层的所述第一和第二栅电极之间的一部分。 此外，从第一和第二栅电极去除氧化层的暴露部分，以暴露第一和第二栅电极的上部，同时保持第一和第二栅电极之间的氧化物层的一部分，以及硅化 执行第一和第二栅电极的暴露的上部。

    Gate silicidation
    7.
    发明授权
    Gate silicidation 有权
    栅极硅化

    公开(公告)号：US09034746B2

    公开(公告)日：2015-05-19

    申请号：US14524023

    申请日：2014-10-27

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Joachim Patzer ,  Ardechir Pakfar ,  Clemens Fitz ,  Dominic Thurmer

    IPC: H01L21/02 ,  H01L21/8234 ,  H01L29/49 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/324 ,  H01L21/28

    CPC classification number: H01L21/823443 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/32053 ,  H01L21/321 ,  H01L21/324 ,  H01L27/0629 ,  H01L27/088 ,  H01L29/4925 ,  H01L29/4933

    Abstract: A method for performing silicidation of gate electrodes includes providing a semiconductor device having first and second transistors with first and second gate electrodes formed on a semiconductor substrate, forming an oxide layer on the first and second gate electrodes and the semiconductor substrate, forming a cover layer on the oxide layer, and back etching the cover layer to expose portions of the oxide layer above the first and second gate electrodes while maintaining a portion of the cover layer between the first and second gate electrodes. Furthermore, the exposed portions of the oxide layer are removed from the first and second gate electrodes to expose upper portions of the first and second gate electrodes, while maintaining a portion of the oxide layer between the first and second gate electrodes, and a silicidation of the exposed upper portions of the first and second gate electrodes is performed.

    Abstract translation: 一种用于执行栅电极的硅化的方法包括提供具有第一和第二晶体管的半导体器件，其中第一和第二栅电极形成在半导体衬底上，在第一和第二栅电极和半导体衬底上形成氧化物层，形成覆盖层 在所述氧化物层上，并且背面蚀刻所述覆盖层以暴露所述第一和第二栅电极之上的所述氧化物层的部分，同时保持所述覆盖层的所述第一和第二栅电极之间的一部分。 此外，从第一和第二栅电极去除氧化层的暴露部分，以暴露第一和第二栅电极的上部，同时保持第一和第二栅电极之间的氧化物层的一部分，以及硅化 执行第一和第二栅极的暴露的上部。

    GATE SILICIDATION
    8.
    发明申请
    GATE SILICIDATION 有权
    盖茨硅胶

    公开(公告)号：US20150044861A1

    公开(公告)日：2015-02-12

    申请号：US14524023

    申请日：2014-10-27

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Joachim Patzer ,  Ardechir Pakfar ,  Clemens Fitz ,  Dominic Thurmer

    IPC: H01L21/8234 ,  H01L21/28 ,  H01L21/321 ,  H01L21/324 ,  H01L29/49 ,  H01L21/3205

    CPC classification number: H01L21/823443 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/32053 ,  H01L21/321 ,  H01L21/324 ,  H01L27/0629 ,  H01L27/088 ,  H01L29/4925 ,  H01L29/4933

    Abstract: A method for performing silicidation of gate electrodes includes providing a semiconductor device having first and second transistors with first and second gate electrodes formed on a semiconductor substrate, forming an oxide layer on the first and second gate electrodes and the semiconductor substrate, forming a cover layer on the oxide layer, and back etching the cover layer to expose portions of the oxide layer above the first and second gate electrodes while maintaining a portion of the cover layer between the first and second gate electrodes. Furthermore, the exposed portions of the oxide layer are removed from the first and second gate electrodes to expose upper portions of the first and second gate electrodes, while maintaining a portion of the oxide layer between the first and second gate electrodes, and a silicidation of the exposed upper portions of the first and second gate electrodes is performed.

    Abstract translation: 一种用于执行栅电极的硅化的方法包括提供具有第一和第二晶体管的半导体器件，其中第一和第二栅电极形成在半导体衬底上，在第一和第二栅电极和半导体衬底上形成氧化物层，形成覆盖层 在所述氧化物层上，并且背面蚀刻所述覆盖层以暴露所述第一和第二栅电极之上的所述氧化物层的部分，同时保持所述覆盖层的所述第一和第二栅电极之间的一部分。 此外，从第一和第二栅电极去除氧化层的暴露部分，以暴露第一和第二栅电极的上部，同时保持第一和第二栅电极之间的氧化物层的一部分，以及硅化 执行第一和第二栅电极的暴露的上部。

    TRANSISTOR ELEMENT WITH GATE ELECTRODE OF REDUCED HEIGHT AND RAISED DRAIN AND SOURCE REGIONS AND METHOD OF FABRICATING THE SAME
    9.
    发明申请
    TRANSISTOR ELEMENT WITH GATE ELECTRODE OF REDUCED HEIGHT AND RAISED DRAIN AND SOURCE REGIONS AND METHOD OF FABRICATING THE SAME 审中-公开

    公开(公告)号：US20190043963A1

    公开(公告)日：2019-02-07

    申请号：US15667755

    申请日：2017-08-03

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Peter Baars ,  Hans-Juergen Thees ,  Clemens Fitz

    IPC: H01L29/66 ,  H01L29/417

    Abstract: A transistor element of a sophisticated semiconductor device includes a gate electrode structure including a metal-containing electrode material instead of the conventionally used highly doped semiconductor material. The metal-containing electrode material may be formed in an early manufacturing stage, thereby reducing overall complexity of patterning the gate electrode structure in approaches in which the gate electrode structure is formed prior to the formation of the drain and source regions. Due to the metal-containing electrode material, high conductivity at reduced parasitic capacitance may be achieved, thereby rendering the techniques of the present disclosure as highly suitable for further device scaling.

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