公开(公告)号：US10593754B2

公开(公告)日：2020-03-17

申请号：US16045267

申请日：2018-07-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar Singh ,  Jerome Ciavatti ,  Jae Gon Lee ,  Josef Watts

IPC: H01L21/265 ,  H01L29/06 ,  H01L21/762

Abstract: Semiconductor structures and methods of forming semiconductor structures. Trench isolation regions arranged to surround an active device region The trench isolation regions extend through a device layer and a buried oxide layer of a silicon-on-insulator wafer into a substrate of the silicon-on-insulator wafer. A well is arranged in the substrate outside of the trench isolation regions, and a doped region is arranged in a portion of the substrate. The doped region is arranged in a portion of the substrate that is located in a horizontal direction adjacent to one of the trench isolation regions and in a vertical direction adjacent to the buried oxide layer. The doped region and the well have the same conductivity type.

公开(公告)号：US10090204B1

公开(公告)日：2018-10-02

申请号：US15609201

申请日：2017-05-31

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Jae Gon Lee

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/08 ,  H01L29/423 ,  H01L29/06 ,  H01L23/535

Abstract: The disclosure is directed to an integrated circuit structure and methods of forming the same. The integrated circuit structure may include: a set of fins within an ILD layer on a substrate; a first gate dielectric over the substrate and extending along opposing sidewalls of each fin in the set of fins, a metal stack adjacent to the first gate dielectric and on the opposing sidewalls of each fin, the metal stack having a first portion over the substrate and a second portion contacting the first gate dielectric and extending along the opposing sidewalls of each fin, wherein at least the first portion of the metal stack and a portion of the first gate dielectric above the substrate is replaced by another dielectric material; a set of epitaxial regions within the ILD layer; and a conductor within the ILD layer and extending over each epitaxial region.

公开(公告)号：US10892338B2

公开(公告)日：2021-01-12

申请号：US16169269

申请日：2018-10-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Ruilong Xie ,  Jae Gon Lee

IPC: H01L29/417 ,  H01L29/08 ,  H01L29/51 ,  H01L29/78 ,  H01L29/66 ,  H01L23/528 ,  H01L21/768 ,  H01L23/522

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a scaled gate contact and source/drain cap and methods of manufacture. The structure includes: a gate structure comprising an active region; source and drain contacts adjacent to the gate structure; a capping material over the source and drain contacts; a gate contact formed directly above the active region of the gate structure and over the capping material; a U-shape dielectric material around the gate contact, above the source and drain contacts; and a contact in direct electrical contact to the source and drain contacts.

公开(公告)号：US20200273953A1

公开(公告)日：2020-08-27

申请号：US16287365

申请日：2019-02-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tao Chu ,  Wei Ma ,  Jae Gon Lee ,  Hong Yu ,  Zhenyu Hu ,  Srikanth Balaji Samavedam

IPC: H01L29/10 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L27/092

Abstract: One illustrative integrated circuit product disclosed herein includes a short-channel transistor device and a long-channel transistor device formed above a semiconductor substrate, wherein a first gate structure for the short-channel transistor device includes a short-channel WFM layer with a first upper surface that is positioned at a first distance above an upper surface of the semiconductor substrate, and wherein a second gate structure for the long-channel transistor device includes a long-channel WFM layer with a second upper surface that is positioned at a second distance above the upper surface of the semiconductor substrate, wherein the first distance is greater than the second distance.

公开(公告)号：US20200066883A1

公开(公告)日：2020-02-27

申请号：US16108152

申请日：2018-08-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yanping Shen ,  Hui Zang ,  Bingwu Liu ,  Manoj Joshi ,  Jae Gon Lee ,  Hsien-Ching Lo ,  Zhaoying Hu

IPC: H01L29/66 ,  H01L21/308 ,  H01L29/78 ,  H01L29/08 ,  H01L21/8234

Abstract: Methods form devices by patterning a lower layer to form a fin, and forming a sacrificial gate along sidewalls of the fin. Such methods form a mask with cut openings on the sacrificial gate and remove sections of the fin and the sacrificial gate exposed through the cut openings to divide the fin into fin portions and create cut areas between the fin portions. Additionally, these methods remove the mask, epitaxially grow source/drains in the cut areas, replace the sacrificial gate with a gate conductor, and form a gate contact on the gate conductor over a center of the fin portions.

公开(公告)号：US20190280105A1

公开(公告)日：2019-09-12

申请号：US15916323

申请日：2018-03-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yanping Shen ,  Hui Zang ,  Hsien-Ching Lo ,  Qun Gao ,  Jerome Ciavatti ,  Yi Qi ,  Wei Hong ,  Yongjun Shi ,  Jae Gon Lee ,  Chun Yu Wong

IPC: H01L29/66 ,  H01L27/092 ,  H01L21/8238

Abstract: Methods form structures that include (among other components) semiconductor fins extending from a substrate, gate insulators contacting channel regions of the semiconductor fins, and gate conductors positioned adjacent the channel regions and contacting the gate insulators. Additionally, epitaxial source/drain material contacts the semiconductor fins on opposite sides of the channel regions, and source/drain conductive contacts contact the epitaxial source/drain material. Also, first insulating spacers are on the gate conductors. The gate conductors are linear conductors perpendicular to the semiconductor fins, and the first insulating spacers are on both sides of the gate conductors. Further, second insulating spacers are on the first insulating spacers; however, the second insulating spacers are only on the first insulating spacers in locations between where the gate conductors intersect the semiconductor fins.

公开(公告)号：US09847391B1

公开(公告)日：2017-12-19

申请号：US15479801

申请日：2017-04-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Jae Gon Lee

IPC: H01L21/00 ,  H01L29/06 ,  H01L29/78 ,  H01L29/165 ,  H01L29/66 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/0673 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0646 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/785

Abstract: Structures involving a field-effect transistor and methods for forming a structure that involves a field-effect transistor. A substrate is provided that has a first conductivity type. A first semiconductor layer having a second conductivity type is formed on the substrate. A second semiconductor layer having the first conductivity type is formed on the first semiconductor layer. A field-effect transistor is formed that includes a fin having a plurality of nanosheet channel layers arranged in a vertical stack on the second semiconductor layer, and a gate structure wrapped about the nanosheet channel layers. The first semiconductor layer defines a first p-n junction with a portion of the substrate, and the second semiconductor layer defines a second p-n junction with the first semiconductor layer. The first p-n junction and the second p-n junction are arranged in vertical alignment with the gate structure and the nanosheet channel layers.

公开(公告)号：US11569356B2

公开(公告)日：2023-01-31

申请号：US17097419

申请日：2020-11-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Ruilong Xie ,  Jae Gon Lee

IPC: H01L29/417 ,  H01L29/78 ,  H01L21/768 ,  H01L29/66 ,  H01L29/08 ,  H01L29/51 ,  H01L23/528 ,  H01L23/522

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a scaled gate contact and source/drain cap and methods of manufacture. The structure includes: a gate structure comprising an active region; source and drain contacts adjacent to the gate structure; a capping material over the source and drain contacts; a gate contact formed directly above the active region of the gate structure and over the capping material; a U-shape dielectric material around the gate contact, above the source and drain contacts; and a contact in direct electrical contact to the source and drain contacts.

公开(公告)号：US10755982B1

公开(公告)日：2020-08-25

申请号：US16508816

申请日：2019-07-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Abu Naser M. Zainuddin ,  Wei Ma ,  Daniel Jaeger ,  Joseph Versaggi ,  Jae Gon Lee ,  Thomas Kauerauf

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/66

Abstract: One illustrative method disclosed herein includes forming 1st and 2nd sacrificial gate structures for, respectively, 1st and 2nd devices, removing 1st and 2nd sacrificial gate electrodes from the 1st and 2nd sacrificial gate structures so as to at least partially define, respectively, 1st and 2nd replacement gate (RMG) cavities, and removing the 2nd sacrificial gate insulation layer from the 2nd RMG cavity while leaving the 1st sacrificial gate insulation layer in position in the 1st RMG cavity. The method also includes forming a conformal gate insulation layer in both the 1st and 2nd RMG cavities, removing the conformal gate insulation layer and the 1st sacrificial gate insulation layer from the 1st RMG cavity while leaving the conformal gate insulation layer in the 2nd RMG cavity, and performing an oxidation process to form an interfacial gate insulation layer only in the 1st RMG cavity.

公开(公告)号：US10553707B1

公开(公告)日：2020-02-04

申请号：US16108152

申请日：2018-08-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yanping Shen ,  Hui Zang ,  Bingwu Liu ,  Manoj Joshi ,  Jae Gon Lee ,  Hsien-Ching Lo ,  Zhaoying Hu

IPC: H01L29/66 ,  H01L21/308 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/78

Abstract: Methods form devices by patterning a lower layer to form a fin, and forming a sacrificial gate along sidewalls of the fin. Such methods form a mask with cut openings on the sacrificial gate and remove sections of the fin and the sacrificial gate exposed through the cut openings to divide the fin into fin portions and create cut areas between the fin portions. Additionally, these methods remove the mask, epitaxially grow source/drains in the cut areas, replace the sacrificial gate with a gate conductor, and form a gate contact on the gate conductor over a center of the fin portions.