公开(公告)号：US09142513B2

公开(公告)日：2015-09-22

申请号：US14645598

申请日：2015-03-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mahbub Rashed ,  Yuansheng Ma ,  Irene Lin ,  Jason Stephens ,  Yunfei Deng ,  Yuan Lei ,  Jongwook K E ,  Roderick Augur ,  Shibly Ahmed ,  Subramani Kengeri ,  Suresh Venkatesan

IPC: H01L23/538 ,  H01L29/78 ,  H01L27/092 ,  H01L27/02

CPC classification number: H01L23/5386 ,  H01L21/76895 ,  H01L21/823871 ,  H01L23/5384 ,  H01L27/0207 ,  H01L27/0924 ,  H01L29/7851 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An approach for providing MOL constructs using diffusion contact structures is disclosed. Embodiments include: providing a first diffusion region in a substrate; providing, via a first lithography process, a first diffusion contact structure; providing, via a second lithography process, a second diffusion contact structure; and coupling the first diffusion contact structure to the first diffusion region and the second diffusion contact structure. Embodiments include: providing a second diffusion region in the substrate; providing a diffusion gap region between the first and second diffusion regions; providing the diffusion contact structure over the diffusion gap region; and coupling, via the diffusion contact structure, the first and second diffusion regions.

公开(公告)号：US08987816B2

公开(公告)日：2015-03-24

申请号：US14519902

申请日：2014-10-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jason Stephens ,  Marc Tarabbia ,  Nader Hindawy ,  Roderick Augur

IPC: H01L21/768 ,  H01L23/48 ,  H01L27/088 ,  H01L29/49 ,  G06F17/50

CPC classification number: H01L23/481 ,  G06F17/5077 ,  H01L21/76877 ,  H01L23/5286 ,  H01L27/088 ,  H01L29/41725 ,  H01L29/4916 ,  H01L2027/11861 ,  H01L2027/11881 ,  H01L2924/0002 ,  Y02T10/82 ,  H01L2924/00

Abstract: A method for forming CA power rails using a three mask decomposition process and the resulting device are provided. Embodiments include forming a horizontal diffusion CA power rail in an active layer of a semiconductor substrate using a first color mask; forming a plurality of vertical CAs in the active layer using second and third color masks, the vertical CAs connecting the CA power rail to at least one diffusion region on the semiconductor substrate, spaced from the CA power rail, wherein each pair of CAs formed by one of the second and third color masks are separated by at least two pitches.

Abstract translation: 提供了使用三掩模分解处理形成CA电力轨道的方法和所得到的装置。 实施例包括使用第一颜色掩模在半导体衬底的有源层中形成水平扩散CA电力轨道; 使用第二和第三颜色掩模在有源层中形成多个垂直CA，垂直CA将CA电力轨连接到半导体衬底上与CA电力轨道间隔开的至少一个扩散区，其中每对CA由 第二和第三彩色掩模中的一个被至少两个间距分开。

公开(公告)号：US10211147B2

公开(公告)日：2019-02-19

申请号：US15643032

申请日：2017-07-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Chanro Park ,  Lei Sun ,  Yi Qi ,  Roderick Augur

IPC: H01L21/00 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L49/02 ,  H01L21/768 ,  H01L21/311 ,  H01L21/3213

Abstract: Methods for fabricating a structure that includes a metal-insulator-metal (MIM) capacitor and structures that include a MIM capacitor. A layer stack is deposited that includes a first conductor layer, a second conductor layer, and a third conductor layer. The layer stack is patterned to define a first electrode of the MIM capacitor from the first conductor layer, a second electrode of the MIM capacitor from the second conductor layer, and a third electrode of the MIM capacitor from the third conductor layer. A via opening is formed that extends vertically through the layer stack. The first electrode is recessed relative to the second electrode to define a cavity that is laterally offset from the via opening. A dielectric inner spacer is formed in the cavity. A conductive via is formed in the first via opening after the dielectric inner spacer is formed.

公开(公告)号：US20190013269A1

公开(公告)日：2019-01-10

申请号：US15643032

申请日：2017-07-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Chanro Park ,  Lei Sun ,  Yi Qi ,  Roderick Augur

IPC: H01L23/522 ,  H01L23/528 ,  H01L49/02 ,  H01L21/768 ,  H01L21/311 ,  H01L21/3213

Abstract: Methods for fabricating a structure that includes a metal-insulator-metal (MIM) capacitor and structures that include a MIM capacitor. A layer stack is deposited that includes a first conductor layer, a second conductor layer, and a third conductor layer. The layer stack is patterned to define a first electrode of the MIM capacitor from the first conductor layer, a second electrode of the MIM capacitor from the second conductor layer, and a third electrode of the MIM capacitor from the third conductor layer. A via opening is formed that extends vertically through the layer stack. The first electrode is recessed relative to the second electrode to define a cavity that is laterally offset from the via opening. A dielectric inner spacer is formed in the cavity. A conductive via is formed in the first via opening after the dielectric inner spacer is formed.