公开(公告)号：US20160035723A1

公开(公告)日：2016-02-04

申请号：US14447193

申请日：2014-07-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng WU ,  Yanxiang LIU

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/45 ,  H01L21/66

CPC classification number: H01L22/14 ,  H01L21/823431 ,  H01L22/34 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/456 ,  H01L2225/06596

Abstract: The disclosure provides methods and devices for separately determining the channel resistance and the extension resistance of a FinFET. An exemplary embodiment includes forming first and second fins parallel to each other, forming at least one fin portion, connecting the first and second fins, forming a gate perpendicular to the first and second fins, over the at least one fin portion, forming a first source and a first drain over the first fin at opposite sides of the gate, and forming a second source and a second drain over the second fin, separate from the first source and drain, at opposite sides of the gate, wherein each of the first and second sources and first and second drains includes an extension region.

Abstract translation: 本公开提供用于单独确定FinFET的沟道电阻和扩展电阻的方法和装置。 一个示例性实施例包括形成彼此平行的第一和第二翅片，形成至少一个翅片部分，连接第一和第二翅片，在至少一个翅片部分上形成垂直于第一和第二翅片的门，形成第一 源极和位于栅极的相对侧的第一鳍片上的第一漏极，并且在栅极的相对侧处在第二鳍片上形成第二源极和第二漏极，该第二源极和第二漏极与第一源极和漏极分离，其中第一 并且第二源和第一和第二排水口包括延伸区域。

公开(公告)号：US20160190252A1

公开(公告)日：2016-06-30

申请号：US14679074

申请日：2015-04-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peijie FENG ,  Yanxiang LIU ,  Shesh Mani PANDEY ,  Jianwei PENG ,  Francis BENISTANT

IPC: H01L29/08 ,  H01L21/265 ,  H01L29/24 ,  H01L21/3065 ,  H01L21/02 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/324

CPC classification number: H01L29/41791 ,  H01L21/02057 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/28512 ,  H01L21/3065 ,  H01L21/324 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/45 ,  H01L29/785

Abstract: A method of forming a source/drain region with abrupt vertical and conformal junction and the resulting device are disclosed. Embodiments include forming a first mask over a fin of a first polarity FET and source/drain regions of the first polarity FET; forming spacers on opposite sides of a fin of a second polarity FET, the second polarity being opposite the first polarity, on each side of a gate electrode; implanting a first dopant into the fin of the second polarity FET; etching a cavity in the fin of the second polarity FET on each side of the gate electrode; removing the first mask; performing rapid thermal anneal (RTA); epitaxially growing a source/drain region of the second polarity FET in each cavity; forming a second mask over the fin of the first polarity FET and source/drain regions of the first polarity FET; and implanting a second dopant in the source/drain regions of the second polarity FET.

Abstract translation: 公开了一种形成具有突然垂直和共形结的源极/漏极区域的方法以及所得到的器件。 实施例包括在第一极性FET的鳍片和第一极性FET的源极/漏极区域上形成第一掩模; 在栅电极的每一侧上在第二极性FET的鳍的相对侧上形成间隔物，第二极性与第一极性相反; 将第一掺杂剂注入到第二极性FET的鳍中; 在栅电极的每一侧蚀刻第二极性FET的鳍的空腔; 去除第一个面罩; 进行快速热退火（RTA）; 在每个空腔中外延生长第二极性FET的源极/漏极区域; 在第一极性FET的鳍片和第一极性FET的源极/漏极区域上形成第二掩模; 以及在所述第二极性FET的源极/漏极区域中注入第二掺杂剂。

公开(公告)号：US20160111322A1

公开(公告)日：2016-04-21

申请号：US14974772

申请日：2015-12-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yanxiang LIU ,  Min-hwa CHI

IPC: H01L21/762 ,  H01L21/225 ,  H01L29/66 ,  H01L21/283

CPC classification number: H01L21/76243 ,  H01L21/2253 ,  H01L21/283 ,  H01L29/66795 ,  H01L29/7849 ,  H01L29/785

Abstract: There is set forth herein in one embodiment a FinFET semiconductor device having a fin extending from a bulk silicon substrate, wherein there is formed wrapped around a portion of the fin a gate, and wherein proximate a channel area of the fin aligned to the gate there is formed a local buried oxide region aligned to the gate. In one embodiment, the local buried oxide region is formed below a channel area of the fin.

公开(公告)号：US20150200298A1

公开(公告)日：2015-07-16

申请号：US14156565

申请日：2014-01-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yanxiang LIU ,  Min-hwa CHI

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/417 ,  H03C3/02 ,  H01L29/161 ,  H01L21/265 ,  H01L21/324 ,  H01L29/66 ,  H01L29/08

CPC classification number: H03C3/145 ,  H01L27/088 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/66356 ,  H01L29/66568 ,  H01L29/66977 ,  H01L29/7391 ,  H01L29/78 ,  H01L29/7848 ,  H03C3/02 ,  H03C3/245 ,  H03D7/125

Abstract: Tunneling field effect transistors and fabrication methods thereof are provided, which include: obtaining a gate structure disposed over a substrate structure; and providing a source region and a drain region within the substrate structure separated by a channel region, the channel region underlying, at least partially, the gate structure, and the providing including: modifying the source region to attain a narrowed source region bandgap; and modifying the drain region to attain a narrowed drain region bandgap, the narrowed source region bandgap and the narrowed drain region bandgap facilitating quantum tunneling of charge carriers from the source region or the drain region to the channel region. Devices including digital modulation circuits with one or more tunneling field effect transistor(s) are also provided.

Abstract translation: 提供隧道场效应晶体管及其制造方法，其包括：获得设置在衬底结构上的栅极结构; 以及在由沟道区分隔开的衬底结构内提供源极区和漏极区，至少部分地位于栅极结构的下方的沟道区，并且所述提供包括：修改源极区以获得变窄的源极区带隙; 并且修改漏极区以获得窄的漏极区带隙，窄的源极区带隙和窄的漏极区带隙，有助于电荷载流子从源区或漏区到沟道区的量子隧穿。 还提供了包括具有一个或多个隧穿场效应晶体管的数字调制电路的装置。

公开(公告)号：US20160225895A1

公开(公告)日：2016-08-04

申请号：US14609105

申请日：2015-01-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xiaoli HE ,  Yanxiang LIU ,  Jerome CIAVATTI ,  Myung Hee NAM

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/311 ,  H01L29/417 ,  H01L29/66 ,  H01L29/10 ,  H01L29/08

CPC classification number: H01L29/7816 ,  H01L21/0332 ,  H01L21/32 ,  H01L29/0653 ,  H01L29/0882 ,  H01L29/1037 ,  H01L29/41775 ,  H01L29/66356 ,  H01L29/66545 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7391 ,  H01L29/7835

Abstract: A non-planar semiconductor structure includes a semiconductor substrate, multiple raised semiconductor structures coupled to the substrate, a drain well in each of the raised structures, and a drain in each drain well. The structure further includes an isolation region in each drain well adjacent the drain, each isolation region reaching to a top surface of the corresponding raised structure, and a conductive center gate on each raised structure, the conductive center gate covering a top surface, a front surface and a back surface thereof, and covering a portion of the isolation region opposite the drain. The isolation regions in the drain wells reaching to the raised structure top surface is a result of preserving the isolation region by covering it during fabrication with an HDP oxide to prevent partial removal.

Abstract translation: 非平面半导体结构包括半导体衬底，耦合到衬底的多个凸起半导体结构，每个凸起结构中的漏极阱和每个漏极阱中的漏极。 该结构还包括在漏极附近的每个漏极阱中的隔离区域，每个隔离区域到达对应的凸起结构的顶表面，以及每个凸起结构上的导电中心栅极，该导电中心栅极覆盖顶部表面，前部 表面和其后表面，并且覆盖与漏极相对的隔离区域的一部分。 到达凸起结构顶表面的漏极阱中的隔离区域是通过在用HDP氧化物制造期间通过覆盖隔离区域来保护隔离区域的结果，以防止部分去除。

公开(公告)号：US20150200251A1

公开(公告)日：2015-07-16

申请号：US14156018

申请日：2014-01-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min-hwa CHI ,  Yanxiang LIU

IPC: H01L29/06 ,  H01L29/78 ,  G11C17/16 ,  H01L29/66

CPC classification number: H01L29/0649 ,  G11C17/16 ,  H01L21/2822 ,  H01L23/5252 ,  H01L27/11206 ,  H01L29/0615 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A process and device are provided for a high-k gate-dielectric operating as a built-in e-fuse. Embodiments include: providing first and second active regions of a transistor, separated by a gate region of the transistor, on a substrate; forming an interfacial layer on the gate region; minimizing the interfacial layer; forming a high-k gate dielectric layer on the interfacial layer to operate as an e-fuse element, the high-k gate dielectric layer and interfacial layer having a combined breakdown voltage less than three times a circuit operating voltage associated with the transistor; and forming a metal gate on the high-k gate dielectric layer.

Abstract translation: 为作为内置电子熔断器操作的高k栅介质提供了一种工艺和器件。 实施例包括：在衬底上提供由晶体管的栅极区分隔开的晶体管的第一和第二有源区; 在栅极区上形成界面层; 最小化界面层; 在所述界面层上形成高k栅介质层，以作为e熔丝元件工作，所述高k栅介质层和界面层的组合击穿电压小于与所述晶体管相关联的电路工作电压的三倍; 并在高k栅极电介质层上形成金属栅极。

公开(公告)号：US20150137235A1

公开(公告)日：2015-05-21

申请号：US14083164

申请日：2013-11-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yanxiang LIU ,  Min-hwa CHI

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L21/76243 ,  H01L21/2253 ,  H01L21/283 ,  H01L29/66795 ,  H01L29/7849 ,  H01L29/785

Abstract: There is set forth herein in one embodiment a FinFET semiconductor device having a fin extending from a bulk silicon substrate, wherein there is formed wrapped around a portion of the fin a gate, and wherein proximate a channel area of the fin aligned to the gate there is formed a local buried oxide region aligned to the gate. In one embodiment, the local buried oxide region is formed below a channel area of the fin.

Abstract translation: 这里在一个实施例中阐述了具有从体硅衬底延伸的翅片的FinFET半导体器件，其中形成为围绕鳍的一部分围绕栅极缠绕，并且其中靠近与栅极对准的鳍的沟道区域 形成与栅极对准的局部掩埋氧化物区域。 在一个实施例中，局部掩埋氧化物区域形成在鳍片的沟道区域的下方。

公开(公告)号：US20160308005A1

公开(公告)日：2016-10-20

申请号：US15189079

申请日：2016-06-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peijie FENG ,  Jianwei PENG ,  Yanxiang LIU ,  Shesh Mani PANDEY ,  Francis BENISTANT

IPC: H01L29/08 ,  H01L29/161 ,  H01L29/417 ,  H01L29/78 ,  H01L21/265 ,  H01L21/268 ,  H01L29/167 ,  H01L29/10

CPC classification number: H01L29/0847 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/268 ,  H01L21/324 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/105 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41725 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A method of forming a source/drain region with an abrupt, vertical and conformal junction and the resulting device are disclosed. Embodiments include forming a gate electrode over and perpendicular to a semiconductor fin; forming first spacers on opposite sides of the gate electrode; forming second spacers on opposite sides of the fin; forming a cavity in the fin adjacent the first spacers, between the second spacers; partially epitaxially growing source/drain regions in each cavity; implanting a first dopant into the partially grown source/drain regions with an optional RTA thereafter; epitaxially growing a remainder of the source/drain regions in the cavities, in situ doped with a second dopant; and implanting a third dopant in the source/drain regions.

Abstract translation: 公开了一种形成具有突然，垂直和共形结的源极/漏极区域的方法以及所得到的器件。 实施例包括在半导体鳍片上方并垂直于半导体鳍片形成栅电极; 在栅电极的相对侧上形成第一间隔物; 在所述翅片的相对侧上形成第二间隔物; 在第二间隔件之间形成邻近第一间隔件的翅片中的空腔; 在每个腔中部分地外延生长源/漏区; 将第一掺杂剂注入部分生长的源极/漏极区域中，其后可选择的RTA; 在空腔中外延生长源/漏区的剩余部分，原位掺杂有第二掺杂剂; 以及在源极/漏极区域中注入第三掺杂剂。

公开(公告)号：US20160284846A1

公开(公告)日：2016-09-29

申请号：US14667872

申请日：2015-03-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yanxiang LIU ,  Min-hwa CHI

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/04 ,  H01L27/092 ,  H01L29/16

CPC classification number: H01L29/0847 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/04 ,  H01L29/083 ,  H01L29/0834 ,  H01L29/7391 ,  H01L29/7847

Abstract: Devices including stacking faults in sources, or sources and drains, of TFETs are disclosed to improve tunneling efficiency. Embodiments may include a tunneling field-effect transistor comprising a substrate; a source and a drain within the substrate; a gate between the source and the drain; and a stacking fault within the source.

Abstract translation: 公开了包括源的堆垛故障或者TFET的源极和漏极的装置，以改善隧道效率。 实施例可以包括隧道场效应晶体管，其包括衬底; 衬底内的源极和漏极; 源极和漏极之间的栅极; 和源内的堆垛故障。

公开(公告)号：US20160104774A1

公开(公告)日：2016-04-14

申请号：US14511769

申请日：2014-10-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jerome CIAVATTI ,  Yanxiang LIU ,  Vara Govindeswara Reddy VAKADA

IPC: H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/1095 ,  H01L29/0653 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/66545 ,  H01L29/66712 ,  H01L29/7809 ,  H01L29/7835

Abstract: A non-planar lateral drift MOS device eliminates the need for a field plate extension, which reduces gate width. In one example, two sources and two comparatively small gates in a raised structure allow for two channels and a dual current with mirrored flows, each traveling into and downward through a center region of a connecting well that connects the substrate with the drain areas and shallow wells containing the source areas, the current then traveling in opposite directions within the substrate region of the connecting well toward the two drains. The source and drain areas may be separate raised structures or isolated areas of a continuous raised structure.

Abstract translation: 非平面横向漂移MOS器件消除了对场板延伸的需要，这减小了栅极宽度。 在一个示例中，凸起结构中的两个源和两个相对较小的栅极允许两个通道和具有镜像流的双电流，每个通道和下游穿过将衬底与漏极区域连接的连接井的中心区域并且向下穿过浅的 包含源极区的阱，然后电流在连接阱的衬底区域内沿相反方向朝着两个漏极行进。 源极和漏极区域可以是分离的凸起结构或连续凸起结构的隔离区域。