公开(公告)号：US20160163702A1

公开(公告)日：2016-06-09

申请号：US14560049

申请日：2014-12-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng WU ,  Yue HU ,  Xin WANG ,  Yong Meng LEE ,  Wen-Pin PENG ,  Lun ZHAO ,  Wei-Hua TONG

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/45 ,  H01L29/417 ,  H01L29/06 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L21/285 ,  H01L29/165 ,  H01L29/08

CPC classification number: H01L27/0922 ,  H01L21/02532 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/31116 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76897 ,  H01L21/823814 ,  H01L21/823828 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

Abstract: Methods for forming a trench silicide without gouging the silicon source/drain regions and the resulting devices are disclosed. Embodiments include forming first and second dummy gates, each with spacers at opposite sides thereof, on a substrate; forming eSiGe source/drain regions at opposite sides of the first dummy gate; forming raised source/drain regions at opposite sides of the second dummy gate; forming a silicon cap on each of the eSiGe and raised source/drain regions; forming an ILD over and between the first and second dummy gates; replacing the first and second dummy gates with first and second HKMG, respectively; forming a contact trench through the ILD into the silicon cap over each of the eSiGe and raised source/drain regions; and forming a silicide over the eSiGe and raised source/drain regions

Abstract translation: 公开了用于形成沟槽硅化物而不使硅源极/漏极区和所得到的器件气蚀的方法。 实施例包括在基板上形成第一和第二伪栅极，每个具有相对侧的间隔物; 在第一伪栅极的相对侧形成eSiGe源极/漏极区; 在所述第二虚拟栅极的相对侧形成凸起的源极/漏极区域; 在每个eSiGe和升高的源极/漏极区域上形成硅帽; 在第一和第二虚拟门之间和之间形成ILD; 分别用第一和第二HKMG代替第一和第二虚拟门; 在每个eSiGe和升高的源极/漏极区域上形成穿过ILD的接触沟槽进入硅帽; 并在eSiGe上形成硅化物并升高源极/漏极区域

公开(公告)号：US20170207118A1

公开(公告)日：2017-07-20

申请号：US14995838

申请日：2016-01-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wen Pin PENG ,  Min-hwa CHI ,  Yue HU

IPC: H01L21/768 ,  H01L29/08 ,  H01L23/535 ,  H01L29/06 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L21/76829 ,  H01L21/28123 ,  H01L21/76897 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/78

Abstract: A starting semiconductor structure for a RMG process includes a semiconductor substrate, transistors in process having dummy gates and electrically isolated by isolation regions. The dummy gates are replaced with metal gates and gate caps, the structure being planarized after replacing the gate. A cap layer is formed over the planarized structure, and trenches are formed through the cap to expose source and drain regions of the transistors, which allows for self-aligned source and drain contacts. Semiconductor structures including the source and drain trenches for self-aligned source/drain contacts are also presented.