公开(公告)号：US11347924B1

公开(公告)日：2022-05-31

申请号：US17572667

申请日：2022-01-11

Applicant: GUANGDONG UNIVERSITY OF TECHNOLOGY

Inventor： Qiang Liu ,  Lijun Wei ,  Xin Chen ,  Duxi Yan ,  Long Li

IPC: G06F30/39 ,  G06F30/392 ,  G06F111/10 ,  G06F111/04

Abstract: A chip layout method based on a minimum total wire length, includes: initializing a total wire length to a preset value, initializing a number of iterations, randomly generating a sequence pair to represent a positional relationship between rectangular circuit modules, inputting the sequence pair to a model, and solving to obtain a sequence pair having a minimum wire length within the number of iterations; changing a field operator of the sequence pair to obtain a new one, inputting the new sequence pair to the model, retaining, if an obtained total wire length is less than the original total wire length, the new sequence pair, or otherwise, abandoning the new sequence pair; repeating the above operation till the number of iterations is reached; and outputting a minimum total wire length, and coordinates of each rectangular circuit module to obtain the chip layout based on the minimum total wire length.