公开(公告)号：US20150022511A1

公开(公告)日：2015-01-22

申请号：US14154911

申请日：2014-01-14

Applicant: Generalplus Technology Inc.

Inventor： Shih-Ming LUO ,  Ming-Hung TSAI

IPC: G09G3/20

CPC classification number: G09G3/2092 ,  G06F1/26 ,  H02J1/00 ,  H02J1/06 ,  H03K17/22 ,  H03K19/00346

Abstract: A method for power-on sequence and a device with a low current power source are provided in the present invention. The method is used for enabling a device including a low current power source, a first circuit module and a second circuit module, wherein the low current power source is used for providing a power voltage. The method includes: switching a low voltage reset signal from a first logic voltage to a second logic voltage when the power voltage rise to a threshold voltage; enabling the first circuit module after a first preset time from the time when the low voltage reset signal switches from the first logic voltage to the second logic voltage; and enabling the second circuit module after a second preset time from the time when the first circuit module is enabled.

Abstract translation: 在本发明中提供了一种用于上电序列的方法和具有低电流电源的装置。 该方法用于启用包括低电流电源，第一电路模块和第二电路模块的装置，其中低电流电源用于提供电源电压。 该方法包括：当电源电压上升到阈值电压时，将低电压复位信号从第一逻辑电压切换到第二逻辑电压; 在从低电压复位信号从第一逻辑电压切换到第二逻辑电压的时间之后的第一预设时间之后启用第一电路模块; 以及在从所述第一电路模块启用时起的第二预设时间之后启用所述第二电路模块。

公开(公告)号：US20140368284A1

公开(公告)日：2014-12-18

申请号：US14166637

申请日：2014-01-28

Applicant: Generalplus Technology Inc.

Inventor： Shih-Ming LUO ,  Min LU

IPC: H03K3/36

CPC classification number: H03K3/0231 ,  H03K3/03 ,  H03K4/501

Abstract: A relaxation oscillator is provided in the present invention. The relaxation oscillator includes a R-S latch, a first delay circuit and a second delay circuit. The input terminal of the first delay circuit is coupled to the Q output terminal of the R-S latch, and the output terminal of the first delay circuit is coupled to the reset terminal of the R-S latch. The input terminal of the second delay circuit is coupled to the inversion Q output terminal of the R-S latch, and the output terminal of the second delay circuit is coupled to the set terminal of the R-S latch. When the input terminal of the first delay circuit inputs a first logic voltage, after a delay time, the output terminal of the first delay circuit outputs a second logic pulse. When the input terminal of the second delay circuit inputs the first logic voltage, after the delay time, the output terminal of the second delay circuit outputs the second logic pulse.

Abstract translation: 在本发明中提供了张弛振荡器。 张弛振荡器包括R-S锁存器，第一延迟电路和第二延迟电路。 第一延迟电路的输入端耦合到R-S锁存器的Q输出端，第一延迟电路的输出端耦合到R-S锁存器的复位端。 第二延迟电路的输入端耦合到R-S锁存器的反相Q输出端，第二延迟电路的输出端耦合到R-S锁存器的设定端。 当第一延迟电路的输入端输入第一逻辑电压时，在延迟时间之后，第一延迟电路的输出端输出第二逻辑脉冲。 当第二延迟电路的输入端输入第一逻辑电压时，在延迟时间之后，第二延迟电路的输出端输出第二逻辑脉冲。