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    AREA AND/OR POWER OPTIMIZATION THROUGH POST-LAYOUT MODIFICATION OF INTEGRATED CIRCUIT (IC) DESIGN BLOCKS
    2.
    发明申请
    AREA AND/OR POWER OPTIMIZATION THROUGH POST-LAYOUT MODIFICATION OF INTEGRATED CIRCUIT (IC) DESIGN BLOCKS 有权

    公开(公告)号：US20170212977A1

    公开(公告)日：2017-07-27

    申请号：US15002550

    申请日：2016-01-21

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Jeanne P. Bickford ,  Alok Chandra ,  Anand Kumaraswamy ,  Sandeep Prajapati ,  Venkatasreekanth Prudvi

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G06F17/5072 ,  G06F17/5077 ,  G06F2217/78 ,  G06F2217/84

    Abstract: Disclosed are integrated circuit (IC) design methods, systems and computer program products that provide for area and/or power optimization through post-layout modification of design blocks. Specifically, a layout for an initial IC design is accessed. This initial IC design incorporates multiple instances of the same design block. Each instance includes a primary input connected to top-level logic for receiving a signal and one or more modifiable periphery sections. A timing analysis is performed to close timing and determine arrival times of the signal at the primary inputs of all instances of the design block, respectively, given the layout. The arrival times are then compared to a preselected threshold arrival time and the modifiable periphery section(s) of any specific instance of the design block having an arrival time that is equal to or less than the preselected threshold arrival time is selectively modified in order to generate an area and/or power optimized integrated circuit design.

    SLEW WINDOW SHIFT PLACEMENT METHOD TO REDUCE HOT SPOTS AND RECOVER VT/AREA
    3.
    发明申请
    SLEW WINDOW SHIFT PLACEMENT METHOD TO REDUCE HOT SPOTS AND RECOVER VT/AREA 审中-公开

    公开(公告)号：US20180089354A1

    公开(公告)日：2018-03-29

    申请号：US15276840

    申请日：2016-09-27

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Alok Chandra ,  Jeanne P. Bickford ,  Venkatasreekanth Prudvi ,  Sandeep Prajapati ,  Anand Kumaraswamy

    IPC: G06F17/50

    CPC classification number: G06F17/5045 ,  G06F17/5031 ,  G06F2217/78 ,  G06F2217/84

    Abstract: Systems and methods for reducing hot spots and recovering Vt/area to improve chip performance in an integrated circuit design. According to the method, physical grid areas for an IC chip are defined and a switching window for library elements of an integrated circuit design in a region of the chip is determined. Points of peak current for library elements within the switching window are determined. A grid area is selected and library elements having additional usable timing margin are identified. The library elements are prioritized, based on location in the grid area according to peak current and usable timing margin. Based on order of priority, the timing of signal paths in the grid area may be adjusted in order to misalign points of peak current and maintain current density in the region below a threshold and/or a library element within the grid area may be changed to recover area within the grid area.

    Electromigration-aware integrated circuit design methods and systems
    5.
    发明授权
    Electromigration-aware integrated circuit design methods and systems 有权

    公开(公告)号：US09740815B2

    公开(公告)日：2017-08-22

    申请号：US14922256

    申请日：2015-10-26

    Applicant: GlobalFoundries Inc.

    Inventor： Jeanne P. Bickford ,  Alok Chandra ,  Anand Kumaraswamy ,  Sandeep Prajapati ,  Venkatasreekanth Prudvi

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G06F17/505 ,  G06F17/5072 ,  G06F17/5077 ,  G06F2217/76 ,  G06F2217/78

    Abstract: Disclosed are electromigration (EM)-aware integrated circuit (IC) design techniques, which consider EM early in the IC design process in order to generate, in a timely manner, an IC design that can be used to manufacture IC chips that will exhibit minimal EM fails for improved IC reliability. Specifically, prior to placement of library elements, EM-relevant information is acquired and used to define protected zones around at least some of the library elements. Once the protected zones are defined, the library elements are placed relative to power rails in a previously designed power delivery network (PDN) and this placement process is performed such that each library element is prevented from being placed in a protected zone around any other library element to avoid EM fails in the PDN. Optionally, this same EM-relevant information is used during subsequent synthesis of a clock distribution network to prevent EM fails therein.

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