公开(公告)号：US20240224515A1

公开(公告)日：2024-07-04

申请号：US18149733

申请日：2023-01-04

Applicant: GlobalFoundries U.S. Inc.

Inventor： Ralf Richter ,  Stefan Dünkel ,  Violetta Sessi

IPC: H10B41/30

CPC classification number: H10B41/30

Abstract: The disclosure provides a structure with a buried doped region for coupling a source line contact to the gate structure of a memory cell. A structure according to the disclosure includes a memory cell having a gate structure extending in a first lateral direction over a substrate. A buried doped region is within the substrate and extends in a second lateral direction from below the gate structure to a portion of the substrate laterally distal to the gate structure. A source line contact is on the portion of the substrate laterally distal to the gate structure. The buried doped region couples the source line contact to the gate structure of the memory cell through a lower surface of the gate structure.

公开(公告)号：US20240332417A1

公开(公告)日：2024-10-03

申请号：US18127041

申请日：2023-03-28

Applicant: GlobalFoundries U.S. Inc.

Inventor： Thomas Melde ,  Ralf Richter ,  Stefan Dünkel

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7816 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/401 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66681

Abstract: Disclosed are embodiments of a semiconductor device and method of forming the device. The device includes a gate with first and second sections on a semiconductor layer. The first section includes first gate dielectric and gate conductor layers and an optional additional gate conductor layer on the first gate conductor layer. The second section includes second gate dielectric and gate conductor layers on the semiconductor layer and further extending onto the top of the first gate conductor layer. The second gate dielectric layer is thinner than the first gate dielectric layer. A gate sidewall spacer is on the first gate conductor layer positioned laterally to a sidewall of the second section (e.g., between the sidewall and the optional additional gate conductor layer). The first and second sections are either electrically connected for biasing with the gate bias voltage or electrically isolated for biasing with different gate bias voltages.

公开(公告)号：US11825663B2

公开(公告)日：2023-11-21

申请号：US17403880

申请日：2021-08-17

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Johannes Müller ,  Thomas Melde ,  Stefan Dünkel ,  Ralf Richter

IPC: H10B53/30 ,  G11C11/22 ,  H10B53/10

CPC classification number: H10B53/30 ,  G11C11/221 ,  G11C11/2275 ,  H10B53/10

Abstract: A nonvolatile memory device is provided, the device comprising a ferroelectric memory capacitor arranged over a first active region contact of a first transistor and a gate contact of a second transistor, whereby the ferroelectric memory capacitor at least partially overlaps a gate of the first transistor.

公开(公告)号：US11631772B2

公开(公告)日：2023-04-18

申请号：US17147684

申请日：2021-01-13

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Thomas Melde ,  Stefan Dünkel ,  Ralf Richter

IPC: H01L27/11521 ,  H01L29/788 ,  H01L29/423 ,  H01L27/12

Abstract: A non-volatile memory (NVM) structure includes a first memory device including: a first inter-poly dielectric defined by an isolation layer over a first semiconductor layer over an insulator layer (SOI) stack over a bulk semiconductor substrate, a first tunneling insulator defined by the insulator layer, a first floating gate defined by the semiconductor layer of the SOI stack, and a first channel region defined in the bulk semiconductor substrate between a source region and a drain region. The memory device may also include a control gate over the SOI stack, an erase gate over a source region in the bulk substrate, and a bitline contact coupled to a drain region in the bulk substrate. The NVM structure may also include another memory device similar to the first memory device and sharing the source region.

公开(公告)号：US20220223740A1

公开(公告)日：2022-07-14

申请号：US17147684

申请日：2021-01-13

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Thomas Melde ,  Stefan Dünkel ,  Ralf Richter

IPC: H01L29/788 ,  H01L27/11521 ,  H01L27/12 ,  H01L29/423

Abstract: A non-volatile memory (NVM) structure includes a first memory device including: a first inter-poly dielectric defined by an isolation layer over a first semiconductor layer over an insulator layer (SOI) stack over a bulk semiconductor substrate, a first tunneling insulator defined by the insulator layer, a first floating gate defined by the semiconductor layer of the SOI stack, and a first channel region defined in the bulk semiconductor substrate between a source region and a drain region. The memory device may also include a control gate over the SOI stack, an erase gate over a source region in the bulk substrate, and a bitline contact coupled to a drain region in the bulk substrate. The NVM structure may also include another memory device similar to the first memory device and sharing the source region.