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    SINGLE ENDED SENSE AMPLIFIER WITH CURRENT PULSE CIRCUIT
    2.
    发明申请
    SINGLE ENDED SENSE AMPLIFIER WITH CURRENT PULSE CIRCUIT 有权

    公开(公告)号：US20250166671A1

    公开(公告)日：2025-05-22

    申请号：US19035131

    申请日：2025-01-23

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Siva Kumar Chinthu ,  Suresh Pasupula ,  Devesh Dwivedi ,  Chunsung Chiang

    IPC: G11C7/06 ,  G11C7/10 ,  G11C7/12

    Abstract: Embodiments of the disclosure provide memory circuit, a sense amplifier and associated method for reading a resistive state in a memory device. The sense amplifier includes a bit cell configurable to a high or low resistance state; a sensing circuit that detects a voltage drop across the bit cell in response to an applied read current during a read operation and generates a high or low logic output at an output node; and a pulse generation circuit that increases the applied read current with an injected current pulse when a low to high transition of the resistive state of the bit cell is detected.

    Single ended sense amplifier with current pulse circuit
    3.
    发明授权
    Single ended sense amplifier with current pulse circuit 有权

    公开(公告)号：US12243614B2

    公开(公告)日：2025-03-04

    申请号：US18046961

    申请日：2022-10-17

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Siva Kumar Chinthu ,  Suresh Pasupula ,  Devesh Dwivedi ,  Chunsung Chiang

    IPC: G11C7/06 ,  G11C7/10 ,  G11C7/12

    Abstract: Embodiments of the disclosure provide memory circuit, a sense amplifier and associated method for reading a resistive state in a memory device. The sense amplifier includes a bit cell configurable to a high or low resistance state; a sensing circuit that detects a voltage drop across the bit cell in response to an applied read current during a read operation and generates a high or low logic output at an output node; and a pulse generation circuit that increases the applied read current with an injected current pulse when a low to high transition of the resistive state of the bit cell is detected.

    SINGLE-STAGE AND MULTI-STAGE VOLTAGE LEVEL SHIFTERS
    4.
    发明申请
    SINGLE-STAGE AND MULTI-STAGE VOLTAGE LEVEL SHIFTERS 有权

    公开(公告)号：US20250023565A1

    公开(公告)日：2025-01-16

    申请号：US18350294

    申请日：2023-07-11

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Siva Kumar Chinthu

    IPC: H03K19/0185

    Abstract: Disclosed structures include a single-stage and a multi-stage voltage level shifter. Each structure includes multiple transistors, which are optionally all symmetric low-voltage transistors, and the structures are configured to avoid operation outside the safe operating area (SOA) of such transistors. The single-stage voltage level shifter and the first stage of the multi-stage voltage level shifter can be essentially identical. In operation, input voltage pulses (including an input voltage pulse transitioning between a first positive voltage (V1) equal to the voltage rating of the transistors and ground) can be received at source nodes of N-type transistors and, in response, output voltage pulses (including an intermediate output voltage pulse transitioning between V1 and a second positive voltage (V2) that is higher than (e.g., double) V1 and an output voltage pulse that transitions between ground and V2) can be output.

    CUSTOMIZABLE LOGIC CELL WITH METHODS TO FORM SAME
    5.
    发明申请
    CUSTOMIZABLE LOGIC CELL WITH METHODS TO FORM SAME 有权

    公开(公告)号：US20240380400A1

    公开(公告)日：2024-11-14

    申请号：US18313427

    申请日：2023-05-08

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Siva Kumar Chinthu ,  Venu Gopal Reddy Ara ,  Devesh Dwivedi

    IPC: H03K19/0185

    Abstract: Embodiments of the disclosure provide a customizable logic cells and related methods to form the same. A structure of the disclosure includes a first pair of complementary transistors connected in series between a first voltage node and a second voltage node. Each transistor of the first pair includes a gate coupled to a first input node. A second pair of complementary transistors is connected in series between the first voltage node and the second voltage node in an opposite orientation from the first pair of complementary transistors. Each transistor of the second pair includes a gate coupled to a second input node. An output line is coupled to a first electrical connection between the first pair complementary transistors and a second electrical connection between the second pair of complementary transistors.

    MULTI-STAGE CHARGE PUMP CIRCUIT INCLUDING VOLTAGE LEVEL SHIFTER FOR CLOCK SIGNAL GENERATION
    9.
    发明申请
    MULTI-STAGE CHARGE PUMP CIRCUIT INCLUDING VOLTAGE LEVEL SHIFTER FOR CLOCK SIGNAL GENERATION 有权

    公开(公告)号：US20250023466A1

    公开(公告)日：2025-01-16

    申请号：US18350316

    申请日：2023-07-11

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Siva Kumar Chinthu ,  Palle Sundar Veerendranath ,  Venu Gopal Reddy Ara ,  Abdul Rajak

    IPC: H02M3/07 ,  H03K19/0185

    Abstract: A disclosed charge pump includes first and second stages and, optionally, additional stage(s). The first stage receives a voltage input (Vin) at a first voltage (V1), CLK1 (GND, V1), and CLK1B (V1, GND), and outputs a first stage voltage output (Vout1) at a second voltage (V2) double V1. A second stage receives Vout1, CLK2 (V1, V2), and CLK2B (V2, V1, and outputs a second stage voltage output (Vout2) at a third voltage (V3) essentially triple V1, and so on. A clock driver supplies CLK1-CLK1B to the first stage and to a clock generator. The clock generator includes: a voltage level shifter, which receives CLK1 and CLK1B and outputs multiple level-shifted voltage output pulses; and a driving circuit, which receives specific ones of the output voltage pulses and outputs CLK2 and CLK2B to the second stage and, if needed, additional voltage level-shifted clock signal-inverted clock signal pairs to any additional stages.

    MULTI-RAIL SENSE CIRCUIT WITH PRE-CHARGE TRANSISTORS AND MEMORY CIRCUIT INCORPORATING THE SENSE CIRCUIT
    10.
    发明公开
    MULTI-RAIL SENSE CIRCUIT WITH PRE-CHARGE TRANSISTORS AND MEMORY CIRCUIT INCORPORATING THE SENSE CIRCUIT 审中-公开

    公开(公告)号：US20240282373A1

    公开(公告)日：2024-08-22

    申请号：US18170925

    申请日：2023-02-17

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Siva Kumar Chinthu ,  Suresh Pasupula ,  Devesh Dwivedi

    IPC: G11C13/00 ,  G11C11/16

    CPC classification number: G11C13/004 ,  G11C11/1673 ,  G11C2013/0054

    Abstract: Disclosed are a sense circuit and memory structure incorporating the sense circuit. The sense circuit is connected to voltage rails at VDD1 and VDD2, respectively, where VDD2˜½*VDD1. During a sensing operation, VDD1 provides power to develop a voltage differential between Vdata and Vref on sense nodes. A voltage comparator samples Vdata and Vref and, based on a detectable voltage differential (minVdiff), outputs a data output value. To increase the speed at which minVdiff is reached, an equalization process is performed at the initiation of the sensing operation and includes using pre-charge transistors to quickly equalize the sense nodes to VDD2. Following equalization, Vdata and Vref only need to be pulled up or down from VDD2. Thus, minVdiff is reached faster and sampling by the voltage comparator can be performed earlier in time, reducing the overall time required for performing the sensing operation and for powering the sense circuit.

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