公开(公告)号：US12170329B2

公开(公告)日：2024-12-17

申请号：US17692218

申请日：2022-03-11

Applicant: GlobalFoundries U.S. Inc.

Inventor： Anupam Dutta ,  Vvss Satyasuresh Choppalli ,  Rajendran Krishnasamy

IPC: H01L29/78 ,  H01L21/3215 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66

Abstract: According to various embodiments, there is provided a MOSFET device. The MOSFET device may include a substrate; a first doped region disposed in the substrate; a second doped region disposed in the substrate, wherein the first doped region and the second doped region are laterally adjacent to each other; a third doped region disposed in the first doped region; a fourth doped region disposed in the second doped region; a gate disposed on the substrate, over the first and second doped regions, and between the third and fourth doped regions; and at least one high resistance region embedded in at least the second doped region, wherein the first doped region has a first conductivity type, wherein the second doped region, the third doped region, and the fourth doped region have a second conductivity type, wherein the first conductivity type and the second conductivity type are different.

公开(公告)号：US12293994B2

公开(公告)日：2025-05-06

申请号：US17955225

申请日：2022-09-28

Applicant: GlobalFoundries U.S. Inc.

Inventor： Vvss Satyasuresh Choppalli ,  Anupam Dutta ,  Rajendran Krishnasamy ,  Robert Gauthier, Jr. ,  Xiang Xiang Lu ,  Anindya Nath

IPC: H01L25/07 ,  H01L21/77 ,  H01L23/14 ,  H01L23/522

Abstract: Structures including multiple semiconductor devices and methods of forming same. The structure comprises a first device structure including a first well and a second well in a semiconductor substrate, a second device structure including a doped region in the semiconductor substrate, and a first high-resistivity region in the semiconductor substrate. The first well has a first conductivity type, the second well has a second conductivity type opposite to the first conductivity type, and the first well adjoins the second well to define a p-n junction. The doped region of the second device structure has the first conductivity type or the second conductivity type. The high-resistivity region has a higher electrical resistivity than the semiconductor substrate, and the high-resistivity region is positioned between the first device structure and the second device structure.

公开(公告)号：US12237407B2

公开(公告)日：2025-02-25

申请号：US17978633

申请日：2022-11-01

Applicant: GlobalFoundries U.S. Inc.

Inventor： Anupam Dutta ,  Rajendran Krishnasamy ,  Vvss Satyasuresh Choppalli ,  Vibhor Jain ,  Robert J. Gauthier, Jr.

IPC: H01L29/737

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors (HBTs) with a buried trap rich region and methods of manufacture. The structure includes: a heterojunction bipolar transistor comprising a collector region, a base region and an emitter region; and at least one non-single-crystal semiconductor region in the collector region of the heterojunction bipolar transistor.

公开(公告)号：US12199147B2

公开(公告)日：2025-01-14

申请号：US17734135

申请日：2022-05-02

Applicant: GlobalFoundries U.S. Inc.

Inventor： Vvss Satyasuresh Choppalli ,  Anupam Dutta ,  Aaron Lee Vallett

IPC: H01L29/10 ,  H01L21/74

Abstract: The present disclosure relates to a semiconductor device including a substrate, a first region disposed in the substrate, a terminal region disposed in the first region, a body contact region disposed in the first region and spaced apart from the terminal region, a dielectric layer disposed on the substrate over the first region between the terminal region and the body contact region, an electrically conductive layer disposed on the dielectric layer, and a continuous metallic layer disposed on the electrically conductive layer and extending to the body contact region, the continuous metallic layer disposed on the body contact region and in physical contact with a top and side portions of the electrically conductive layer. The semiconductor device may additionally include a body contact interconnect disposed on a portion of the continuous metallic layer over the electrically conductive layer.

公开(公告)号：US20240105683A1

公开(公告)日：2024-03-28

申请号：US17955225

申请日：2022-09-28

Applicant: GlobalFoundries U.S. Inc.

Inventor： Vvss Satyasuresh Choppalli ,  Anupam Dutta ,  Rajendran Krishnasamy ,  Robert Gauthier, JR. ,  Xiang Xiang Lu ,  Anindya Nath

IPC: H01L25/07 ,  H01L21/77 ,  H01L23/14 ,  H01L23/522

CPC classification number: H01L25/072 ,  H01L21/77 ,  H01L23/147 ,  H01L23/5228

Abstract: Structures including multiple semiconductor devices and methods of forming same. The structure comprises a first device structure including a first well and a second well in a semiconductor substrate, a second device structure including a doped region in the semiconductor substrate, and a first high-resistivity region in the semiconductor substrate. The first well has a first conductivity type, the second well has a second conductivity type opposite to the first conductivity type, and the first well adjoins the second well to define a p-n junction. The doped region of the second device structure has the first conductivity type or the second conductivity type. The high-resistivity region has a higher electrical resistivity than the semiconductor substrate, and the high-resistivity region is positioned between the first device structure and the second device structure.