公开(公告)号：US12272619B2

公开(公告)日：2025-04-08

申请号：US17971087

申请日：2022-10-21

Applicant: Google LLC

Inventor： Jorge Padilla ,  Madhusudan K. Iyengar ,  Connor Burgess ,  Padam Jain ,  Yuan Li ,  Feini Zhang

IPC: H01L23/433 ,  H01L25/065

Abstract: Systems and methods for utilizing the dead space around the periphery of a chip for sealing a direct liquid cooled module are disclosed. One of the functions of a direct liquid cooled module is to provide cooling liquid to components located on a chip. A groove member for receiving a sealing member may be applied to the top surface of the chip. The groove member may be directly deposited to the top surface or coupled thereto via an adhesive and/or epoxy. The groove member may be in the form of opposing sidewalls or a u-shaped structure each of which form a partial enclosure for receipt of the sealing member. The groove member may be located entirely within the dead space or at least partially within the dead space and partially within a central area in which the chip components are located. The sealing member may be an O-ring or a gasket.

公开(公告)号：US11721641B2

公开(公告)日：2023-08-08

申请号：US16877730

申请日：2020-05-19

Applicant: Google LLC

Inventor： Madhusudan K. Iyengar ,  Connor Burgess ,  Padam Jain ,  Emad Samadiani ,  Yuan Li

IPC: H01L23/00 ,  H01L23/16 ,  H01L23/473

CPC classification number: H01L23/562 ,  H01L23/16 ,  H01L23/473

Abstract: A weight optimized stiffener for use in a semiconductor device is disclosed herein. In one example, the stiffener is made of AlSiC for its weight and thermal properties. An O-ring provides sealing between a top surface of the stiffener and a component of the semiconductor device and adhesive provides sealing between a bottom surface of the stiffener and another component of the semiconductor device. The stiffener provides warpage control for a lidless package while enabling direct liquid cooling of a chip or substrate.

公开(公告)号：US20210378106A1

公开(公告)日：2021-12-02

申请号：US17333570

申请日：2021-05-28

Applicant: Google LLC

Inventor： Madhusudan K. Iyengar ,  Christopher Malone ,  Woon-Seong Kwon ,  Emad Samadiani ,  Melanie Beauchemin ,  Padam Jain ,  Teckgyu Kang ,  Yuan Li ,  Connor Burgess ,  Norman Paul Jouppi ,  Nicholas Stevens-Yu ,  Yingying Wang

IPC: H05K3/34 ,  H05K7/20 ,  H01L23/00

Abstract: A method of manufacturing a chip assembly comprises joining an in-process unit to a printed circuit board; reflowing a bonding material disposed between and electrically connecting the in-process unit with the printed circuit board, the bonding material having a first reflow temperature; and then joining a heat distribution device to the plurality of semiconductor chips using a thermal interface material (“TIM”) having a second reflow temperature that is lower than the first reflow temperature. The in-process unit further comprises a substrate having an active surface, a passive surface, and contacts exposed at the active surface; an interposer electrically connected to the substrate; a plurality of semiconductor chips overlying the substrate and electrically connected to the substrate through the interposer, and a stiffener overlying the substrate and having an aperture extending therethrough, the plurality of semiconductor chips being positioned within the aperture.

公开(公告)号：US20240038620A1

公开(公告)日：2024-02-01

申请号：US17876813

申请日：2022-07-29

Applicant: Google LLC

Inventor： Yingshi Tang ,  Yingying Wang ,  Padam Jain ,  Emad Samadiani ,  Sudharshan Sugavanesh Udhayakumar ,  Madhusudan K. Iyengar

IPC: H01L23/367 ,  H01L23/467 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/3677 ,  H01L23/467 ,  H01L23/3128 ,  H01L24/18 ,  H01L2924/1811 ,  H01L2224/16227

Abstract: A pin fin placement assembly utilized to form pin fins in a thermal dissipating feature is provided. The pin fin placement assembly may place the pin fins on an IC die disposed in the IC package. The pin fin placement assembly may assist massively placing the pin fins with desired profiles and numbers on desired locations of the IC die. The plurality of pin fins is formed in a first plurality of apertures in the pin fin placement assembly. A thermal process is then performed to solder the plurality of pin fins on the IC die.

公开(公告)号：US20230163048A1

公开(公告)日：2023-05-25

申请号：US17570647

申请日：2022-01-07

Applicant: Google LLC

Inventor： Yingying Wang ,  Emad Samadiani ,  Madhusudan K. Iyengar ,  Padam Jain ,  Xiaojin Wei ,  Teckgyu Kang ,  Sudharshan Sugavanesh Udhayakumar ,  Yingshi Tang

IPC: H01L23/46 ,  H01L21/56

CPC classification number: H01L23/46 ,  H01L21/56 ,  H01L24/73

Abstract: An IC die includes a temperature control element suitable for three-dimensional IC package with enhanced thermal control and management. The temperature control element may assist temperature control of the IC die when in operation. In one example, the temperature control element may have a plurality of thermal dissipating features disposed on a first surface of the IC die to efficiently control and dissipate the thermal energy from the IC die when in operation. A second surface opposite to the first surface of the IC die may include a plurality of devices, such as semiconductors transistors, devices, electrical components, circuits, or the like, that may generate thermal energy when in operation. The temperature control element may provide an IC die with high efficiency of heat dissipation that is suitable for 3D IC package structures and requirements.

公开(公告)号：US11488890B2

公开(公告)日：2022-11-01

申请号：US16880417

申请日：2020-05-21

Applicant: Google LLC

Inventor： Jorge Padilla ,  Madhusudan K. Iyengar ,  Connor Burgess ,  Padam Jain ,  Yuan Li ,  Feini Zhang

IPC: H01L23/433 ,  H01L25/065

Abstract: Systems and methods for utilizing the dead space around the periphery of a chip for sealing a direct liquid cooled module are disclosed. One of the functions of a direct liquid cooled module is to provide cooling liquid to components located on a chip. A groove member for receiving a sealing member may be applied to the top surface of the chip. The groove member may be directly deposited to the top surface or coupled thereto via an adhesive and/or epoxy. The groove member may be in the form of opposing sidewalls or a u-shaped structure each of which form a partial enclosure for receipt of the sealing member. The groove member may be located entirely within the dead space or at least partially within the dead space and partially within a central area in which the chip components are located. The sealing member may be an O-ring or a gasket.

公开(公告)号：US20210366841A1

公开(公告)日：2021-11-25

申请号：US16877730

申请日：2020-05-19

Applicant: Google LLC

Inventor： Madhusudan K. Iyengar ,  Connor Burgess ,  Padam Jain ,  Emad Samadiani ,  Yuan Li

IPC: H01L23/00 ,  H01L23/16 ,  H01L23/473

Abstract: A weight optimized stiffener for use in a semiconductor device is disclosed herein. In one example, the stiffener is made of AlSiC for its weight and thermal properties. An O-ring provides sealing between a top surface of the stiffener and a component of the semiconductor device and adhesive provides sealing between a bottom surface of the stiffener and another component of the semiconductor device. The stiffener provides warpage control for a lidless package while enabling direct liquid cooling of a chip or substrate.

公开(公告)号：US12243802B2

公开(公告)日：2025-03-04

申请号：US18634198

申请日：2024-04-12

Applicant: Google LLC

Inventor： Madhusudan K. Iyengar ,  Christopher Malone ,  Woon-Seong Kwon ,  Emad Samadiani ,  Melanie Beauchemin ,  Padam Jain ,  Teckgyu Kang ,  Yuan Li ,  Connor Burgess ,  Norman Paul Jouppi ,  Nicholas Stevens-Yu ,  Yingying Wang

IPC: H01L23/00 ,  B23K1/00 ,  H01L23/373 ,  H05K3/34 ,  H05K7/20 ,  H01L25/065

Abstract: A method of manufacturing a chip assembly comprises joining an in-process unit to a printed circuit board; reflowing a bonding material disposed between and electrically connecting the in-process unit with the printed circuit board, the bonding material having a first reflow temperature; and then joining a heat distribution device to the plurality of semiconductor chips using a thermal interface material (“TIM”) having a second reflow temperature that is lower than the first reflow temperature. The in-process unit further comprises a substrate having an active surface, a passive surface, and contacts exposed at the active surface; an interposer electrically connected to the substrate; a plurality of semiconductor chips overlying the substrate and electrically connected to the substrate through the interposer, and a stiffener overlying the substrate and having an aperture extending therethrough, the plurality of semiconductor chips being positioned within the aperture.

公开(公告)号：US20230260931A1

公开(公告)日：2023-08-17

申请号：US18139025

申请日：2023-04-25

Applicant: Google LLC

Inventor： Madhusudan K. Iyengar ,  Connor Burgess ,  Padam Jain ,  Emad Samadiani ,  Yuan Li

IPC: H01L23/00 ,  H01L23/16 ,  H01L23/473

CPC classification number: H01L23/562 ,  H01L23/16 ,  H01L23/473

Abstract: A weight optimized stiffener for use in a semiconductor device is disclosed herein. In one example, the stiffener is made of AlSiC for its weight and thermal properties. An O-ring provides sealing between a top surface of the stiffener and a component of the semiconductor device and adhesive provides sealing between a bottom surface of the stiffener and another component of the semiconductor device. The stiffener provides warpage control for a lidless package while enabling direct liquid cooling of a chip or substrate.

公开(公告)号：US20210366807A1

公开(公告)日：2021-11-25

申请号：US16880417

申请日：2020-05-21

Applicant: Google LLC

Inventor： Jorge Padilla ,  Madhusudan K. Iyengar ,  Connor Burgess ,  Padam Jain ,  Yuan Li ,  Feini Zhang

IPC: H01L23/433 ,  H01L25/065

Abstract: Systems and methods for utilizing the dead space around the periphery of a chip for sealing a direct liquid cooled module are disclosed. One of the functions of a direct liquid cooled module is to provide cooling liquid to components located on a chip. A groove member for receiving a sealing member may be applied to the top surface of the chip. The groove member may be directly deposited to the top surface or coupled thereto via an adhesive and/or epoxy. The groove member may be in the form of opposing sidewalls or a u-shaped structure each of which form a partial enclosure for receipt of the sealing member. The groove member may be located entirely within the dead space or at least partially within the dead space and partially within a central area in which the chip components are located. The sealing member may be an O-ring or a gasket.