公开(公告)号：US11625061B2

公开(公告)日：2023-04-11

申请号：US17349488

申请日：2021-06-16

Applicant: Graphcore Limited

Inventor： Simon Douglas Chambers ,  Stephen Felix ,  Ian Malcolm King

IPC: G06F1/08 ,  G06F1/12 ,  G06F1/10

Abstract: Two clocks, a fast clock and a slow clock are provided for clocking a processing unit. A plurality of frequency settings, referred to as gears, are defined for the two clock. Each of these gears indicates a maximum frequency for the fast clock and a minimum frequency for the slow clock, such that the gap between the two frequencies may be kept to a manageable level so as to reduce transients upon switching between the two clocks. The system switches between the gears as required. In response to a determination to increase the frequency of the clock signal, a higher gear is selected at which the maximum and minimum frequencies defined for that gear are higher than the previous selected gear.