公开(公告)号：US10453516B2

公开(公告)日：2019-10-22

申请号：US15899514

申请日：2018-02-20

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Reza M Bacchus ,  Melvin K Benedict ,  Stephen F Contreras ,  Eric L Pope ,  Chi K Sides ,  Chun-Pin Huang

IPC: G11C5/06 ,  G11C5/10 ,  G11C11/4074 ,  G11C5/14 ,  G11C5/04

Abstract: An example device in accordance with an aspect of the present disclosure includes a memory module having a voltage regulator module (VRM) to receive input power and deliver output power to components of the memory module at a first power plane. A sufficient number of stitching capacitors are to couple the first power plane to a second power plane.

公开(公告)号：US09928897B2

公开(公告)日：2018-03-27

申请号：US15500070

申请日：2015-02-27

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Reza M. Bacchus ,  Melvin K. Benedict ,  Stephen F. Contreras ,  Eric L. Pope ,  Chi K. Sides ,  Chun-Pin Huang

IPC: G11C5/06 ,  G11C11/4074 ,  G11C5/10

CPC classification number: G11C11/4074 ,  G11C5/04 ,  G11C5/06 ,  G11C5/10 ,  G11C5/14 ,  G11C5/147 ,  G11C11/401

Abstract: An example device in accordance with an aspect of the present disclosure includes a memory module having a voltage regulator module (VRM) to receive input power and deliver output power to components of the memory module at a first power plane. At least one stitching capacitor is to couple the first power plane to a second power plane.