公开(公告)号：US20240046988A1

公开(公告)日：2024-02-08

申请号：US17876471

申请日：2022-07-28

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： GIACOMO PEDRETTI ,  Catherine GRAVES ,  Sergey SEREBRYAKOV ,  John Paul STRACHAN

IPC: G11C15/04 ,  G11C7/06 ,  G11C7/16 ,  H03M1/18

CPC classification number: G11C15/04 ,  G11C7/062 ,  G11C7/16 ,  H03M1/181

Abstract: Embodiments of the disclosure provide a system, method, or computer readable medium for providing a differentiable content addressable memory (aCAM) that implements an analog input analog storage and analog output learning memory. The analog output of the differentiable CAM can provide input to a learning algorithm, which may compute the gradients in comparison to historic values and reduce data inaccuracies and power consumption.

公开(公告)号：US20230137079A1

公开(公告)日：2023-05-04

申请号：US17514847

申请日：2021-10-29

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： GIACOMO PEDRETTI ,  JOHN PAUL STRACHAN ,  CATHERINE GRAVES

IPC: G11C27/00 ,  G11C15/04

Abstract: Embodiments of the disclosure provide a system, method, or computer readable medium for programming a target analog voltage range of an analog content addressable memory (aCAM) row. The method may comprise calculating a threshold current sufficient to switch a sense amplifier (SA) on and discharge a match line (ML) connected to a cell of the aCAM; and based on calculating the threshold current, programming a match threshold value by setting a memristor conductance in association with the target analog voltage range applied to a data line (DL) input. The target analog voltage range may comprise a target analog voltage range vector.

公开(公告)号：US20240249787A1

公开(公告)日：2024-07-25

申请号：US18347318

申请日：2023-07-05

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： GIACOMO PEDRETTI ,  Ron M. Roth

IPC: G11C27/00

CPC classification number: G11C27/005

Abstract: Examples of the presently disclosed technology provide “tree-CAMs” specially constructed to implement decision trees more efficiently—namely with less hardware (i.e., fewer memristors and transistors), less power consumption, and less memristor programming time than existing aCAMs used to implement decision trees. A tree-CAM realizes these optimizations by leveraging a shared comparison sub-circuit that stores a threshold shared among evaluable conditions for multiple root-to-leaf-paths of a decision tree. The threshold may be evaluated against a common feature of a feature vector. The shared comparison sub-circuit may comprise just a single memristor programmed to store the threshold. Accordingly, the tree-CAM can represent/implement evaluable conditions (sharing a common threshold and evaluated against a common feature) across multiple root-to-leaf paths of a decision tree using just a single memristor—thus reducing the number of memristors required to implement the decision tree.

公开(公告)号：US20240029792A1

公开(公告)日：2024-01-25

申请号：US17872882

申请日：2022-07-25

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： TOBIAS FREDERIC ZIEGLER ,  RON M. ROTH ,  GIACOMO PEDRETTI ,  LUCA BUONANNO ,  PEDRO HENRIQUE ROCHA BRUEL ,  CATHERINE GRAVES

IPC: G11C15/04 ,  G11C16/12 ,  G11C16/10 ,  H03K19/017

CPC classification number: G11C15/04 ,  G11C16/12 ,  G11C16/102 ,  H03K19/01742

Abstract: Examples increase precision for aCAMs by converting an input signal (x) received by a circuit into a first analog voltage signal (V(xMSB)) representing the most significant bits of the input signal (x) and a second analog voltage signal (V(xLSB)) representing the least significant bits of the input signal (x). By dividing the input signal (x) bit-wise into the first analog voltage signal (V(xMSB)) and the second analog voltage signal (V(xLSB)), the circuit can utilize aCAM sub-circuits implementing a combination of Boolean operations to search the input signal (x) against 22*M programmable levels, where “M” represents the number of programmable bits for each aCAM sub-circuit. Thus, using similar circuit hardware, example circuits square the number of programmable levels of conventional aCAMs (which generally only have 2M programmable levels). Accordingly, examples provide new aCAMs that can carry out more complex computations than conventional aCAMs of comparable cost, size, and power consumption.

公开(公告)号：US20230197151A1

公开(公告)日：2023-06-22

申请号：US17555260

申请日：2021-12-17

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： CATHERINE GRAVES ,  GIACOMO PEDRETTI ,  SERGEY SEREBRYAKOV ,  JOHN PAUL STRACHAN

IPC: G11C13/00 ,  G11C15/04 ,  G06N7/00

CPC classification number: G11C13/004 ,  G11C13/0069 ,  G11C13/0026 ,  G11C13/0028 ,  G11C15/04 ,  G06N7/005

Abstract: Systems and methods are provided for employing analog content addressable memory (aCAMs) to achieve low latency complex distribution sampling. For example, an aCAM core circuit can include an aCAM array. Amplitudes of a probability distribution function are mapped to a width of one or more aCAM cells in each row of the aCAM array. The aCAM core circuit can also include a resistive random access memory (RRAM) storing lookup information, such as information used for processing a model. By randomly selecting columns to search of the aCAM array, the mapped probability distribution function is sampled in a manner that has low latency. The aCAM core circuit can accelerate the sampling step in methods relying on sampling from arbitrary probability distributions, such as particle filter techniques. A hardware architecture for an aCAM Particle Filter that utilizes the aCAM core circuit as a central structure is also described.

公开(公告)号：US20250077584A1

公开(公告)日：2025-03-06

申请号：US18460425

申请日：2023-09-01

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： JOHN MOON ,  GIACOMO PEDRETTI ,  CATHERINE GRAVES

IPC: G06F16/903

Abstract: Examples of the presently disclosed technology provide hardware accelerators (referred to herein as treeShap-aCAMs) that compute Shapley values with improved speed/efficiency leveraging the unique parallel search and analog capabilities of aCAMs. The parallel search capability of a treeShap-aCAM enables evaluation of all root-to-leaf paths of a decision tree (programmed into separate rows of the treeShap-aCAM) in a single clock cycle, greatly reducing time required to compute Shapley values. Relatedly, a treeShap-aCAM's ability to store/evaluate analog values (as opposed to merely binary values), can reduce footprint and hardware (e.g., reduce the number of CAM cells) required to perform Shapley value computations. Accordingly, treeShap-aCAMs can compute Shapley values more rapidly/efficiently than other types of hardware accelerators that e.g., implement algorithms that traverse root-to-leaf paths of decision trees node-to-node.

公开(公告)号：US20240363163A1

公开(公告)日：2024-10-31

申请号：US18308990

申请日：2023-04-28

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： RON M. ROTH ,  LUCA BUONANNO ,  GIACOMO PEDRETTI ,  CATHERINE GRAVES

IPC: G11C15/04 ,  G11C13/00

CPC classification number: G11C15/046 ,  G11C13/0069

Abstract: Systems and methods are provided for implementing a low power and area ternary content addressable memory (TCAM). An example of a TCAM comprises a match line, and a plurality of TCAM cells connected along the match line. Each TCAM cell stores a state of a threshold value. The TCAM cells are configured to pull down a signal over the match line in response to inequality between an input search and the threshold value. The plurality of TCAM cells comprises a number of TCAM cells that is less than the threshold value. The input values can be encoded according to a first encoding scheme and the threshold value can be encoded according to one of a second and a third encoding scheme based on an inequality check mapped to the plurality of TCAM cells.

公开(公告)号：US20240111490A1

公开(公告)日：2024-04-04

申请号：US17953595

申请日：2022-09-27

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： CATHERINE GRAVES ,  GIACOMO PEDRETTI

IPC: G06F7/544 ,  G06F17/16 ,  G11C15/04

CPC classification number: G06F7/5443 ,  G06F17/16 ,  G11C15/04

Abstract: Systems and methods are provided for employing a current input analog content addressable memory (CI-aCAM). The CI-aCAM is particularly structured as aCAM that allows the analog signal that is input into the aCAM cell to be received as current. A larger hardware architecture that combines two core analog compute circuits, namely a dot product engine (DPE) circuit for matrix multiplications and an aCAM circuit for search operations can also be realized using the disclosed CI-aCAM. For instance, a DPE circuit, which output current signals, can be directly connected with the input of a CI-aCAM, which is designed to receive current signals in a manner that eliminates conversion steps and circuits (e.g., analog to digital and current to voltage). By leveraging CI-aCAMs, a combined DPE-aCAM hardware architecture can be a realized as a substantially compact structure.

公开(公告)号：US20230410903A1

公开(公告)日：2023-12-21

申请号：US17841542

申请日：2022-06-15

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： GIACOMO PEDRETTI ,  TOBIAS FREDERIC ZIEGLER ,  THOMAS VAN VAERENBERGH ,  CATHERINE GRAVES

IPC: G11C15/04 ,  H03K19/20

CPC classification number: G11C15/046 ,  H03K19/20

Abstract: The disclosure generally provides for a method of solving a K-SAT problem. The method comprises programming one or more clauses of a Boolean expression for a K-SAT problem written in negated disjunctive normal form (DNF) to a ternary-CAM (TCAM) array comprising columns and rows of TCAM cells. The method further includes applying an interpretation comprising one or more binary variables expected to solve the Boolean expression as an input along the columns to the TCAM array, returning a binary value for each clause, randomly selecting one matched match line, determining a selected clause from one or more violated clause, and altering one or more literals within the interpretation using a break count for each variable of the selected clause.