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    DUAL USE MICROELECTROMECHANICAL SYSTEM (MEMS) DEVICE
    2.
    发明申请
    DUAL USE MICROELECTROMECHANICAL SYSTEM (MEMS) DEVICE 有权

    公开(公告)号：US20250047509A1

    公开(公告)日：2025-02-06

    申请号：US18661373

    申请日：2024-05-10

    Applicant: Honeywell International Inc.

    Inventor： Kenneth H. Heffner ,  Peter L. Cousseau ,  James L. Tucker ,  Donald Patrick Horkheimer

    IPC: H04L9/32 ,  B81B3/00 ,  H04L9/08

    Abstract: A system that includes: a microelectromechanical system (MEMS) device for generating an output signal at an output of the MEMS device, the MEMS device receiving at least one input signal at an input of the MEMS device; a storage medium configured to store a signal injection function and an output generation function; and a processor, in communication with the MEMS device and the storage medium, the processor configured to run the signal injection function to selectively modify the at least one input signal to produce a modified input signal and to provide the modified input signal to the input of the MEMS device, and that is configured to run an output generation function to extract a random component and a unique component from the output signal, wherein the random component and the unique component are generated by the MEMS device based on the modified at least one input signal.

    Wafer trust via location locked circuit layout with measurable integrity
    3.
    发明授权
    Wafer trust via location locked circuit layout with measurable integrity 有权

    公开(公告)号：US11276678B2

    公开(公告)日：2022-03-15

    申请号：US16813375

    申请日：2020-03-09

    Applicant: Honeywell International Inc.

    Inventor： James L. Tucker

    IPC: G06F7/50 ,  H01L27/02 ,  H01L21/66 ,  G06F30/30

    Abstract: Techniques to determine whether the design of integrated circuit (IC) has been tampered with during wafer manufacturing by using an enhanced library and layout methodology. The enhanced library may include location sensitive cells networked together in a mesh architecture where paths through the mesh can be used to detect relative position of location sensitive cells. The techniques further include algorithms that fill any unused space on an IC with additional elements from the enhanced library to minimize the opportunity to modify the IC by including additional circuit function or manipulating the layout. By physically locking down the circuit placement such that there is no available area and gives improved ability to detect changes in the physical location behavior of the circuit, therefore reduces the risk that unauthorized circuit manipulation will go undetected.

    CONFIGURATION BASED CRYPTOGRAPHIC KEY GENERATION
    6.
    发明申请
    CONFIGURATION BASED CRYPTOGRAPHIC KEY GENERATION 审中-公开

    公开(公告)号：US20180131528A1

    公开(公告)日：2018-05-10

    申请号：US15346487

    申请日：2016-11-08

    Applicant: Honeywell International Inc.

    Inventor： John D. Profumo ,  Thomas Cordella ,  James L. Tucker

    IPC: H04L9/32 ,  H04L9/08 ,  H04L9/06

    Abstract: In some examples, a programmable device may load configuration data into a configuration storage to configure programmable logic of the programmable device. The programmable device may include a key generation logic that may read at least a portion of the configuration data from the configuration storage. The key generation logic may generate a cryptographic key based at least in part on the at least a portion of the configuration data read from the configuration storage.

    Systems and methods for a wafer scale atomic clock
    7.
    发明授权
    Systems and methods for a wafer scale atomic clock 有权
    晶圆级原子钟的系统和方法

    公开(公告)号：US09312869B2

    公开(公告)日：2016-04-12

    申请号：US14059698

    申请日：2013-10-22

    Applicant: Honeywell International Inc.

    Inventor： Jeffrey James Kriz ,  James L. Tucker ,  Kenneth H. Heffner ,  Robert Compton

    IPC: H03L7/26 ,  G04F5/14

    CPC classification number: H03L7/26 ,  G04F5/14

    Abstract: Systems and methods for a wafer scale atomic clock are provided. In at least one embodiment, a wafer scale device comprises a first substrate; a cell layer joined to the first substrate, the cell layer comprising a plurality of hermetically isolated cells, wherein separate measurements are produced for each cell in the plurality of hermetically isolated cells; and a second substrate joined to the cell layer, wherein the first substrate and the second substrate comprise electronics to control the separate measurements, wherein the separate measurements are combined into a single measurement.

    Abstract translation: 提供了用于晶片级原子钟的系统和方法。 在至少一个实施例中，晶片秤装置包括第一基板; 连接到所述第一基底的细胞层，所述细胞层包含多个密封分离的细胞，其中对所述多个密闭分离的细胞中的每个细胞产生单独的测量; 以及连接到所述电池层的第二衬底，其中所述第一衬底和所述第二衬底包括用于控制所述单独测量的电子器件，其中所述单独测量被组合成单个测量。

    SYSTEMS AND METHODS FOR A WAFER SCALE ATOMIC CLOCK
    8.
    发明申请
    SYSTEMS AND METHODS FOR A WAFER SCALE ATOMIC CLOCK 有权
    用于尺度原子钟的系统和方法

    公开(公告)号：US20150109061A1

    公开(公告)日：2015-04-23

    申请号：US14059698

    申请日：2013-10-22

    Applicant: Honeywell International Inc.

    Inventor： Jeffrey James Kriz ,  James L. Tucker ,  Kenneth H. Heffner ,  Robert Compton

    IPC: H03L7/26

    CPC classification number: H03L7/26 ,  G04F5/14

    Abstract: Systems and methods for a wafer scale atomic clock are provided. In at least one embodiment, a wafer scale device comprises a first substrate; a cell layer joined to the first substrate, the cell layer comprising a plurality of hermetically isolated cells, wherein separate measurements are produced for each cell in the plurality of hermetically isolated cells; and a second substrate joined to the cell layer, wherein the first substrate and the second substrate comprise electronics to control the separate measurements, wherein the separate measurements are combined into a single measurement.

    Abstract translation: 提供了用于晶片级原子钟的系统和方法。 在至少一个实施例中，晶片秤装置包括第一基板; 连接到所述第一基底的细胞层，所述细胞层包含多个密封分离的细胞，其中对所述多个密闭分离的细胞中的每个细胞产生单独的测量; 以及连接到所述电池层的第二衬底，其中所述第一衬底和所述第二衬底包括用于控制所述单独测量的电子器件，其中所述单独测量被组合成单个测量。

    Configuration based cryptographic key generation
    9.
    发明授权
    Configuration based cryptographic key generation 有权

    公开(公告)号：US10708073B2

    公开(公告)日：2020-07-07

    申请号：US15346487

    申请日：2016-11-08

    Applicant: Honeywell International Inc.

    Inventor： John D. Profumo ,  Thomas Cordella ,  James L. Tucker

    IPC: H04L9/32 ,  H04L9/06 ,  H04L9/08

    Abstract: In some examples, a programmable device may load configuration data into a configuration storage to configure programmable logic of the programmable device. The programmable device may include a key generation logic that may read at least a portion of the configuration data from the configuration storage. The key generation logic may generate a cryptographic key based at least in part on the at least a portion of the configuration data read from the configuration storage.

    WAFER TRUST VIA LOCATION LOCKED CIRCUIT LAYOUT WITH MEASURABLE INTEGRITY
    10.
    发明申请
    WAFER TRUST VIA LOCATION LOCKED CIRCUIT LAYOUT WITH MEASURABLE INTEGRITY 审中-公开

    公开(公告)号：US20200212031A1

    公开(公告)日：2020-07-02

    申请号：US16813375

    申请日：2020-03-09

    Applicant: Honeywell International Inc.

    Inventor： James L. Tucker

    IPC: H01L27/02 ,  H01L21/66 ,  G06F30/30

    Abstract: Techniques to determine whether the design of integrated circuit (IC) has been tampered with during wafer manufacturing by using an enhanced library and layout methodology. The enhanced library may include location sensitive cells networked together in a mesh architecture where paths through the mesh can be used to detect relative position of location sensitive cells. The techniques further include algorithms that fill any unused space on an IC with additional elements from the enhanced library to minimize the opportunity to modify the IC by including additional circuit function or manipulating the layout. By physically locking down the circuit placement such that there is no available area and gives improved ability to detect changes in the physical location behavior of the circuit, therefore reduces the risk that unauthorized circuit manipulation will go undetected.

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