公开(公告)号：US20140044229A1

公开(公告)日：2014-02-13

申请号：US13964647

申请日：2013-08-12

Applicant: HannStar Display Corp.

Inventor： Chien-Ting CHAN ,  Chung-Lin CHANG ,  Kuo-Sheng LEE

IPC: G11C19/28

CPC classification number: G11C19/28 ,  G09G3/20 ,  G09G3/3674 ,  G09G2310/0286 ,  G11C19/18 ,  G11C19/184

Abstract: A shift register and a voltage adjusting circuit and method thereof are disclosed. The voltage adjusting circuit includes a first input terminal, a second input terminal, a transistor, a first capacitor, a second capacitor, and an output terminal. The first input terminal receives a second clock signal. The second input terminal receives a fourth clock signal. The transistor has a source electrode, a drain electrode, and a gate electrode. The source electrode is coupled to ground and the gate electrode is coupled to the second input terminal. The first capacitor is coupled between the drain electrode and the first input terminal. One end of second capacitor is coupled between the first capacitor and drain electrode, and the other end of second capacitor is coupled between the second input terminal and gate electrode. The output terminal is coupled between the first capacitor and drain electrode to output an adjusted voltage.

Abstract translation: 公开了一种移位寄存器和电压调节电路及其方法。 电压调节电路包括第一输入端子，第二输入端子，晶体管，第一电容器，第二电容器和输出端子。 第一输入端接收第二时钟信号。 第二输入端接收第四时钟信号。 晶体管具有源电极，漏电极和栅电极。 源电极耦合到地，栅电极耦合到第二输入端。 第一电容器耦合在漏电极和第一输入端之间。 第二电容器的一端耦合在第一电容器和漏电极之间，第二电容器的另一端耦合在第二输入端子和栅电极之间。 输出端子耦合在第一电容器和漏电极之间以输出调节的电压。

公开(公告)号：US20140232964A1

公开(公告)日：2014-08-21

申请号：US14192243

申请日：2014-02-27

Applicant: HANNSTAR DISPLAY CORP.

Inventor： Chun-Chin TSENG ,  Ya-Wen LEE ,  Kuo-Wen PAN ,  Chien-Ting CHAN

IPC: G02F1/133

CPC classification number: H03K17/161 ,  G09G3/3677 ,  G09G3/3696

Abstract: An integrated gate driver circuit includes a control circuit, a plurality of drive stages and a plurality of discharge transistors. The control circuit is configured to output a plurality of clock signals within a frame period and to output a discharge enabling signal within a blanking period of the frame period. Each of the drive stages receives the clock signals and includes an output terminal configured to output a gate driving signal. Each of the discharge transistors is coupled to the output terminal of one of the drive stages and discharges the output terminal according to the discharge enabling signal thereby eliminating the voltage fluctuation of the output terminal in the blanking period.

Abstract translation: 集成栅极驱动器电路包括控制电路，多个驱动级和多个放电晶体管。 控制电路被配置为在帧周期内输出多个时钟信号，并在帧周期的消隐期间内输出放电使能信号。 每个驱动级接收时钟信号，并且包括被配置为输出栅极驱动信号的输出端子。 每个放电晶体管耦合到一个驱动级的输出端，并根据放电使能信号放电输出端，从而消除了在消隐期间输出端的电压波动。