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    Memory system and method for transferring data therein
    1.
    发明授权
    Memory system and method for transferring data therein 有权
    用于在其中传输数据的存储器系统和方法

    公开(公告)号：US07831797B2

    公开(公告)日：2010-11-09

    申请号：US11862915

    申请日：2007-09-27

    Applicant: Hermann Ruckerbauer

    Inventor： Hermann Ruckerbauer

    IPC: G06F12/00

    CPC classification number: G11C7/1018 ,  G06F13/1684

    Abstract: A memory system is functionally designed so that, despite operation without an error correction device, memory chips of a memory module that are actually provided for error correction are concomitantly used for the data transfer. A control device is configured to receive, store and transfer data packets to and from a first and second set of memory chips. Transfer of an internal packet data from the control device to memory takes place such that a first record is stored in a second set of memory chips and additional records are stored in the first set of memory chips. In preferred embodiments, data is allocated in the second set of memory chips such that at least one additional transfer step takes place to the second set of memory chips compared with transfers to the first set of memory chips. In the additional transfer step(s), the first set of memory chips is masked from receiving data.

    Abstract translation: 存储器系统在功能上被设计成使得尽管在没有纠错装置的情况下进行操作，但实际提供用于纠错的存储器模块的存储器芯片被同时用于数据传输。 控制装置被配置为接收，存储和传送数据分组到第一和第二组存储器芯片。 将内部分组数据从控制设备传送到存储器进行，使得第一记录被存储在第二组存储器芯片中，并且附加记录被存储在第一组存储器芯片中。 在优选实施例中，在第二组存储器芯片中分配数据，使得与传送到第一组存储器芯片相比，至少一个额外的转移步骤发生到第二组存储器芯片。 在附加传送步骤中，第一组存储器芯片被从接收数据中被掩蔽。

    Method of refreshing data in a storage location based on heat dissipation level and system thereof
    2.
    发明授权
    Method of refreshing data in a storage location based on heat dissipation level and system thereof 有权
    基于散热水平及其系统刷新存储位置中的数据的方法

    公开(公告)号：US07768857B2

    公开(公告)日：2010-08-03

    申请号：US11949639

    申请日：2007-12-03

    Applicant: Hermann Ruckerbauer

    Inventor： Hermann Ruckerbauer

    IPC: G11C7/04

    CPC classification number: G11C11/406 ,  G11C7/04 ,  G11C11/40626 ,  G11C2211/4061

    Abstract: An integrated device comprising a storage location, wherein data stored in the storage location is repeatedly refreshed with a first predetermined refresh rate during a first period of time. The first period of time provides a first predetermined duration. After the end of the first period of time, the data is repeatedly refreshed with a second predetermined refresh rate.

    Abstract translation: 一种包括存储位置的集成设备，其中存储在所述存储位置中的数据在第一时间段期间以第一预定刷新率重复地刷新。 第一时间段提供第一预定持续时间。 在第一时间段结束之后，数据以第二预定刷新率反复刷新。

    MULTI MASTER DRAM ARCHITECTURE
    3.
    发明申请
    MULTI MASTER DRAM ARCHITECTURE 有权
    多主体DRAM架构

    公开(公告)号：US20100077157A1

    公开(公告)日：2010-03-25

    申请号：US12235063

    申请日：2008-09-22

    Applicant: Peter Gregorius ,  Thomas Hein ,  Martin Maier ,  Hermann Ruckerbauer ,  Thilo Schaffroth ,  Ralf Schedel ,  Wolfgang Spirkl ,  Johannes Stecker

    Inventor： Peter Gregorius ,  Thomas Hein ,  Martin Maier ,  Hermann Ruckerbauer ,  Thilo Schaffroth ,  Ralf Schedel ,  Wolfgang Spirkl ,  Johannes Stecker

    IPC: G06F12/00 ,  G06F13/14

    CPC classification number: G06F13/1605 ,  G06F13/1684 ,  Y02D10/14

    Abstract: Embodiments of the invention provide a memory device that may be accessed by a plurality of controllers or processor cores via respective ports of the memory device. Each controller may be coupled to a respective port of the memory device via a data bus. Each port of the memory device may be associated a predefined section of memory, thereby giving each controller access to a distinct section of memory without interference from other controllers. A common command/address bus may couple the plurality of controllers to the memory device. Each controller may assert an active signal on a memory access control bus to gain access to the command/address bus to initiate a memory access. In some embodiments, the memory device may be a package comprising a plurality of stacked memory dies.

    Abstract translation: 本发明的实施例提供一种存储器件，其可以经由存储器件的相应端口被多个控制器或处理器核存取。 每个控制器可以经由数据总线耦合到存储器设备的相应端口。 存储器设备的每个端口可以与存储器的预定义部分相关联，从而使每个控制器访问不同部分的存储器，而不受其他控制器的干扰。 公共命令/地址总线可以将多个控制器耦合到存储器设备。 每个控制器可以在存储器访问控制总线上断言有效信号以获得对命令/地址总线的访问以启动存储器访问。 在一些实施例中，存储器件可以是包括多个堆叠的存储器管芯的封装。

    Re-driving CAwD and rD signal lines
    8.
    发明授权
    Re-driving CAwD and rD signal lines 失效
    重新启动CAwD和rD信号线

    公开(公告)号：US07414917B2

    公开(公告)日：2008-08-19

    申请号：US11192335

    申请日：2005-07-29

    Applicant: Hermann Ruckerbauer ,  Simon Muff ,  Christian Weiss ,  Peter Gregorius

    Inventor： Hermann Ruckerbauer ,  Simon Muff ,  Christian Weiss ,  Peter Gregorius

    IPC: G11C8/00

    CPC classification number: G11C5/04 ,  G11C5/06 ,  H05K1/142

    Abstract: Semiconductor memory modules and semiconductor memory systems using the same are described herein. The modules divide a conventional DIMM into a series of separate, smaller memory modules. Each memory module includes at least one semiconductor memory chip arranged on a substrate; CAwD signal input lines arranged on the substrate in a first predetermined line number and connecting one of the semiconductor memory chips to CAwD input signal pins on the substrate; and rD signal output lines arranged on the substrate in a second predetermined line number and connecting the one or a last semiconductor memory to a second number of rD output signal pins of the substrate. In a semiconductor memory system including the semiconductor memory modules, each memory module is separately connected to a memory controller by the CAwD signal input lines and the rD signal output lines in a respective point-to-point fashion.

    Abstract translation: 本文描述了使用其的半导体存储器模块和半导体存储器系统。 这些模块将常规DIMM分成一系列独立的较小内存模块。 每个存储器模块包括布置在衬底上的至少一个半导体存储器芯片; CAwD信号输入线，以第一预定行号排列在基板上，并将半导体存储器芯片之一连接到基板上的CAwD输入信号引脚; 和rD信号输出线，以第二预定行号排列在基板上，并将一个或最后一个半导体存储器连接到基板的第二数量的rD输出信号引脚。 在包括半导体存储器模块的半导体存储器系统中，每个存储器模块通过CAwD信号输入线和rD信号输出线分别以点对点的方式连接到存储器控制器。

    Semiconductor memory device including a signal control device and method of operating the same
    9.
    发明授权
    Semiconductor memory device including a signal control device and method of operating the same 有权
    包括信号控制装置的半导体存储装置及其操作方法

    公开(公告)号：US07404136B2

    公开(公告)日：2008-07-22

    申请号：US11182063

    申请日：2005-07-15

    Applicant: Hermann Ruckerbauer ,  Dominique Savignac

    Inventor： Hermann Ruckerbauer ,  Dominique Savignac

    IPC: H03M13/00

    CPC classification number: G11C7/1006 ,  G06F11/1052 ,  G11C29/42 ,  G11C2207/104

    Abstract: A semiconductor memory device including semiconductor memory cells with at least one memory cell capable of either acting as a storage device for ECC information or of acting as a redundant memory cell is provided. The semiconductor memory device further includes a signal control device for signaling if the at least one memory cell is to be used either as a storage device or as a redundant memory cell. A method of operating a semiconductor memory device is also provided including the steps of registering a status of a signal device and, depending on the status of the signal device, operating the at least one memory cell either as a storing device for ECC information or as a redundant memory cell.

    Abstract translation: 提供一种半导体存储器件，其包括具有至少一个存储单元的半导体存储单元，所述至少一个存储单元可以充当用于ECC信息的存储器件或用作冗余存储器单元。 半导体存储器件还包括信号控制装置，用于发信号通知至少一个存储单元是作为存储装置还是用作冗余存储单元。 还提供了一种操作半导体存储器件的方法，包括以下步骤：注册信号器件的状态，并且根据信号器件的状态，操作至少一个存储器单元作为ECC信息的存储设备或者作为 冗余存储单元。

    Semiconductor memory module
    10.
    发明授权
    Semiconductor memory module 失效
    半导体存储器模块

    公开(公告)号：US07386696B2

    公开(公告)日：2008-06-10

    申请号：US10887019

    申请日：2004-07-08

    Applicant: Andreas Jakobs ,  Hermann Ruckerbauer ,  Maksim Kuzmenka

    Inventor： Andreas Jakobs ,  Hermann Ruckerbauer ,  Maksim Kuzmenka

    IPC: G06F12/00

    CPC classification number: G11C5/063

    Abstract: The invention relates to a semiconductor memory module having a plurality of memory chips arranged in at least one row and at least one buffer chip which drives and receives clock signals and command and address signals to the memory chips and data signals to and from the memory chips via a clock, address, command and data bus inside the module and which forms an interface to an external primary memory bus. The semiconductor memory module has an even number of buffer chips arranged on it and all of the memory chips are connected to two respective buffer chips at least by one signal line type from a signal group and just to one of the two buffer chips by the remaining signal lines from the group. The sum of the electrical signal propagation times for the actuating signals via their lines from one buffer chip to a respective one of the memory chips and the electrical signal propagation times for the data signals from this memory chip to the other buffer chip during the read operation is the same for all of the memory chips, and control means for controlling the respective data write and read operation to or from the memory chips are provided in order to drive the clock signals and command and address signals in the same respective direction as the data signals via the bus inside the module when data are being written and read.

    Abstract translation: 本发明涉及一种半导体存储器模块，其具有布置在至少一行的多个存储器芯片和至少一个缓冲器芯片，该缓冲器芯片驱动并接收时钟信号，以及将命令和寻址信号存储到存储器芯片以及从存储器芯片传送数据信号 通过模块内的时钟，地址，命令和数据总线，并形成与外部主存储器总线的接口。 半导体存储器模块具有布置在其上的偶数个缓冲器芯片，并且所有存储器芯片至少通过一个信号线类型从信号组连接到两个相应的缓冲器芯片，并且仅剩下两个缓冲器芯片之一 来自该组的信号线。 在读取操作期间，通过其线从一个缓冲芯片到相应的一个存储器芯片的致动信号的电信号传播时间和从该存储器芯片到另一个缓冲器芯片的数据信号的电信号传播时间之和 对于所有存储器芯片是相同的，并且提供用于控制到存储器芯片或从存储器芯片的相应数据写入和读取操作的控制装置，以便以与数据相同的相同方向驱动时钟信号和命令和寻址信号 当数据被写入和读取时通过模块内的总线发送信号。

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