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    NETWORK SWITCH WITH HYBRID ARCHITECTURE
    1.
    发明申请
    NETWORK SWITCH WITH HYBRID ARCHITECTURE 有权

    公开(公告)号：US20250112876A1

    公开(公告)日：2025-04-03

    申请号：US18480217

    申请日：2023-10-03

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Duncan Roweth ,  Timothy J. Johnson ,  Abdulla M. Bataineh ,  Jonathan Paul Beecroft

    IPC: H04L49/90 ,  H04L49/00 ,  H04L49/101

    Abstract: A network switch has a packet pulling architecture, and also supports packet pushing. In an example implementation, a device includes: an output buffer; a data crossbar connected to the output buffer; an input buffer connected to the data crossbar; an input queue; a request crossbar connected to the input queue; and an output queue. The input queue is configured to transfer a packet from the input buffer to the output buffer over the data crossbar in response to the packet being eligible for packet pushing, and to send a push request in parallel with transferring the packet to the output buffer. The output queue is configured to receive the push request from the input queue over the request crossbar, and to control reading of the packet from the output buffer in response to granting the push request

    SYSTEM AND METHOD FOR FACILITATING EFFICIENT HOST MEMORY ACCESS FROM A NETWORK INTERFACE CONTROLLER (NIC)
    7.
    发明申请
    SYSTEM AND METHOD FOR FACILITATING EFFICIENT HOST MEMORY ACCESS FROM A NETWORK INTERFACE CONTROLLER (NIC) 有权

    公开(公告)号：US20220197831A1

    公开(公告)日：2022-06-23

    申请号：US17594647

    申请日：2020-03-23

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Igor Gorodetsky ,  Hess M. Hodge ,  Timothy J. Johnson

    IPC: G06F13/16 ,  G06F13/42

    Abstract: A network interface controller (NIC) capable of efficient memory access is provided. The NIC can be equipped with an operation logic block, a signaling logic block, and a tracking logic block. The operation logic block can maintain an operation group associated with packets requesting an operation on a memory segment of a host device of the NIC. The signaling logic block can determine whether a packet associated with the operation group has arrived at or departed from the NIC. Furthermore, the tracking logic block can determine that a request for releasing the memory segment has been issued. The tracking logic block can then determine whether at least one packet associated with the operation group is under processing in the NIC. If no packet associated with the operation group is under processing in the NIC, tracking logic block can notify the host device that the memory segment can be released.

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