公开(公告)号：US20080158978A1

公开(公告)日：2008-07-03

申请号：US11962216

申请日：2007-12-21

Applicant: Hideki NISHIYAMA

Inventor： Hideki NISHIYAMA

IPC: G11C16/06 ,  G11C7/00

CPC classification number: G11C7/065 ,  G11C7/1036 ,  G11C29/1201 ,  G11C29/40 ,  G11C2029/3202

Abstract: A memory read circuit includes k sense amplifiers provided for respective k bit lines and reading out data from their corresponding bit lines, where k is a natural number, a shift register that includes k flip-flops connected in cascade and arranged to hold outputs from corresponding sense amplifiers, and to output the outputs from the k sense amplifiers as serial data, and expected value setting section arranged to store in the k flip-flops expected value data on the outputs from the corresponding sense amplifiers, and a determination section arranged to determine whether the expected value data stored in the flip-flops matches the outputs from the corresponding sense amplifiers.

Abstract translation: 存储器读取电路包括为各个k位线提供的k个读出放大器，并从其对应的位线读出数据，其中k是自然数，移位寄存器包括级联连接的k个触发器，并被布置为保持相应的输出 感测放大器，并且将来自k个读出放大器的输出作为串行数据输出，以及期望值设置部分，被布置成存储在k个触发器中来自相应的读出放大器的输出的期望值数据;以及确定部， 存储在触发器中的期望值数据是否匹配来自对应读出放大器的输出。