公开(公告)号：US20210081347A1

公开(公告)日：2021-03-18

申请号：US16896464

申请日：2020-06-09

Applicant: Huazhong University of Science and Technology

Inventor： Xiaofei LIAO ,  Fan ZHANG ,  Long ZHENG ,  Hai JIN ,  Zhiyuan SHAO

IPC: G06F13/40 ,  G06F9/50 ,  G06F9/48

Abstract: A graph processing optimization method that addresses the problems such as the low computation-to-communication ratio in graph environments, and high communication overhead as well as load imbalance in heterogeneous environments for graph processing. The method reduces communication overhead between accelerators by optimizing graph partitioning so as to improve system scalability.

公开(公告)号：US20250139005A1

公开(公告)日：2025-05-01

申请号：US18893397

申请日：2024-09-23

Applicant: Huazhong University of Science and Technology ,  ZHEJIANG LAB

Inventor： Zhiyuan SHAO ,  Sitong LU ,  Xiaofei LIAO ,  Hai JIN

IPC: G06F12/0802

Abstract: A cache-designing method using cache lines to record cache-miss information is provided, wherein cache lines and cache-miss information are stored in a common storage space by means of shared storage. Tags of cache lines, as well as cache lines and cache-miss information, are stored separately in different static random-access memories, wherein multiple independent memories are used for tags, while a single memory is for cache lines and cache-miss information. A request-processing pipeline and a response-processing pipeline are constructed to be parallelable and used respectively for processing memory-access requests and for processing memory-response data. As compared to existing non-blocking cache designs that support plenty of miss status holding registers, the present disclosure allows storage sharing between cache data and cache-miss information, and leverages dual-port feature of static random-access memories in FPGA, so as to design separate pipelines to achieve memory access respectively for memory-access request processing and for memory-response data processing.