中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

58 records (took 0.021 seconds)

    Semiconductor memory device having a redundancy area
    3.
    发明授权
    Semiconductor memory device having a redundancy area 有权
    具有冗余区域的半导体存储器件

    公开(公告)号：US08614925B2

    公开(公告)日：2013-12-24

    申请号：US12814776

    申请日：2010-06-14

    Applicant: Joonmin Park ,  Beakhyung Cho ,  Kwangjin Lee ,  Hye-Jin Kim

    Inventor： Joonmin Park ,  Beakhyung Cho ,  Kwangjin Lee ,  Hye-Jin Kim

    IPC: G11C7/00

    CPC classification number: G11C29/785 ,  G11C29/808

    Abstract: Provided is a semiconductor memory device. The semiconductor memory includes a main area and a redundancy area. The main area includes a plurality of memory blocks sharing a write bit line and a read bit line. The redundancy area includes a plurality of redundancy memory blocks sharing a redundancy write bit line and a redundancy read bit line. The redundancy area is provided to replace a component in the main area having a defect.

    Abstract translation: 提供了一种半导体存储器件。 半导体存储器包括主区域和冗余区域。 主区域包括共享写入位线和读取位线的多个存储器块。 冗余区域包括共享冗余写位线和冗余读位线的多个冗余存储块。 提供冗余区域以替换具有缺陷的主区域中的部件。

    Non-volatile memory device using variable resistance element with an improved write performance
    5.
    发明授权
    Non-volatile memory device using variable resistance element with an improved write performance 有权
    使用可变电阻元件的非易失性存储器件具有改进的写入性能

    公开(公告)号：US08194447B2

    公开(公告)日：2012-06-05

    申请号：US12314513

    申请日：2008-12-11

    Applicant: Hye-Jin Kim ,  Kwang-Jin Lee ,  Du-Eung Kim ,  Hung-Jun An

    Inventor： Hye-Jin Kim ,  Kwang-Jin Lee ,  Du-Eung Kim ,  Hung-Jun An

    IPC: G11C16/04

    CPC classification number: G11C7/1078 ,  G11C5/14 ,  G11C7/1096 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/72

    Abstract: A non-volatile memory device using a variable resistive element includes a memory cell array having a plurality of non-volatile memory cells, a first voltage generator generating a first voltage, a voltage pad receiving an external voltage that has a level higher than the first voltage, a sense amplifier supplied with the first voltage and reading data from the non-volatile memory cells selected from the memory cell array, and a write driver supplied with the external voltage and writing data to the non-volatile memory cells selected from the memory cell array.

    Abstract translation: 使用可变电阻元件的非易失性存储器件包括具有多个非易失性存储器单元的存储单元阵列，产生第一电压的第一电压发生器，接收高于第一电压的电平的外部电压的电压焊盘 电压，提供有第一电压的读出放大器和从存储单元阵列中选择的非易失性存储器单元读取数据，以及提供有外部电压的写入驱动器，并将数据写入从存储器中选择的非易失性存储器单元 单元格阵列。

    SEMICONDUCTOR MEMORY DEVICE HAVING A REDUNDANCY AREA
    7.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE HAVING A REDUNDANCY AREA 有权
    具有冗余区域的半导体存储器件

    公开(公告)号：US20100329053A1

    公开(公告)日：2010-12-30

    申请号：US12814776

    申请日：2010-06-14

    Applicant: Joonmin Park ,  Beakhyung Cho ,  Kwangjin Lee ,  Hye-Jin Kim

    Inventor： Joonmin Park ,  Beakhyung Cho ,  Kwangjin Lee ,  Hye-Jin Kim

    IPC: G11C29/04 ,  G11C8/00

    CPC classification number: G11C29/785 ,  G11C29/808

    Abstract: Provided is a semiconductor memory device. The semiconductor memory includes a main area and a redundancy area. The main area includes a plurality of memory blocks sharing a write bit line and a read bit line. The redundancy area includes a plurality of redundancy memory blocks sharing a redundancy write bit line and a redundancy read bit line. The redundancy area is provided to replace a component in the main area having a defect.

    Abstract translation: 提供了一种半导体存储器件。 半导体存储器包括主区域和冗余区域。 主区域包括共享写位线和读位线的多个存储块。 冗余区域包括共享冗余写位线和冗余读位线的多个冗余存储块。 提供冗余区域以替换具有缺陷的主区域中的部件。

    Target detecting system and method
    8.
    发明授权
    Target detecting system and method 失效
    目标检测系统及方法

    公开(公告)号：US07688999B2

    公开(公告)日：2010-03-30

    申请号：US11287936

    申请日：2005-11-28

    Applicant: Kye-Kyung Kim ,  Soo-Hyun Cho ,  Hye-Jin Kim ,  Jae-Yeon Lee

    Inventor： Kye-Kyung Kim ,  Soo-Hyun Cho ,  Hye-Jin Kim ,  Jae-Yeon Lee

    IPC: G06K9/00

    CPC classification number: H04N5/232 ,  G06K9/00362 ,  G06T7/246

    Abstract: A target detecting system and method for detecting a target from an input image is provided. According to the target detecting system and method, when a target is detected from an input image and there are moving areas in the input image, camera movement parameters are obtained, image frames are transformed, and movement candidate areas are extracted from the image frame and the previous input image frame. In addition, image feature information is extracted from the input image, and based on the movement candidate areas and the image feature information a shape of the target is extracted. Therefore, the target can be exactly and rapidly extracted and tracked.

    Abstract translation: 提供了一种从输入图像中检测目标的目标检测系统和方法。 根据目标检测系统和方法，当从输入图像检测到目标并且在输入图像中存在移动区域时，获得相机移动参数，变换图像帧，并且从图像帧中提取移动候选区域，并且 以前的输入图像帧。 此外，从输入图像中提取图像特征信息，并且基于移动候选区域和图像特征信息，提取目标的形状。 因此，可以准确，快速地提取和跟踪目标。

    Bias voltage generator and method generating bias voltage for semiconductor memory device
    9.
    发明授权
    Bias voltage generator and method generating bias voltage for semiconductor memory device 有权
    用于半导体存储器件的偏置电压发生器和产生偏置电压的方法

    公开(公告)号：US07548467B2

    公开(公告)日：2009-06-16

    申请号：US11955562

    申请日：2007-12-13

    Applicant: Hye-Jin Kim ,  Kwang-Jin Lee ,  Woo-Yeong Cho ,  Mu-Hui Park

    Inventor： Hye-Jin Kim ,  Kwang-Jin Lee ,  Woo-Yeong Cho ,  Mu-Hui Park

    IPC: G11C5/14

    CPC classification number: G11C13/004 ,  G11C5/147 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0038 ,  G11C16/30 ,  G11C2013/0054 ,  G11C2213/72

    Abstract: There are provided a bias voltage generator, a semiconductor memory device having the bias voltage generator, and a method for generating the bias voltage. The bias voltage generator which generates the bias voltage to control a sensing current supplied to a memory cell for sensing data is characterized in that the bias voltage is output in response to an input voltage being applied, so that a slope of the bias voltage to the input voltage is different in at least two sections divided corresponding to a level of the input voltage.

    Abstract translation: 提供了偏置电压发生器，具有偏置电压发生器的半导体存储器件以及用于产生偏置电压的方法。 产生用于控制提供给存储单元的感测电流以感测数据的偏置电压的偏置电压发生器的特征在于，响应于所施加的输入电压而输出偏置电压，使得偏置电压的斜率 至少两个部分的输入电压不同，对应于输入电压的电平。

    Magneto-resistive RAM having multi-bit cell array structure
    10.
    发明授权
    Magneto-resistive RAM having multi-bit cell array structure 有权
    具有多位单元阵列结构的磁阻RAM

    公开(公告)号：US07463509B2

    公开(公告)日：2008-12-09

    申请号：US11260602

    申请日：2005-10-27

    Applicant: Hye-Jin Kim ,  Woo-Yeong Cho ,  Hyung-Rok Oh

    Inventor： Hye-Jin Kim ,  Woo-Yeong Cho ,  Hyung-Rok Oh

    IPC: G11C11/00

    CPC classification number: H03L7/0812 ,  B82Y10/00 ,  G11C11/15 ,  G11C11/16 ,  G11C11/5607 ,  G11C2211/5615 ,  H01L27/228 ,  H03L7/0891

    Abstract: A magnetic random access memory (RAM) with a multi-bit cell array structure includes an access transistor formed on a substrate, first through third resistance-variable elements, and first through third current supplying lines. The first through third resistance-variable elements are disposed between a bit line and the access transistor, and electrically connected to each other. The first through third current supplying lines are stacked alternately with the first through third resistance-variable elements. The first through third resistance-variable elements have equal resistances.

    Abstract translation: 具有多比特单元阵列结构的磁随机存取存储器（RAM）包括形成在基片上的存取晶体管，第一至第三电阻可变元件以及第一至第三电流线。 第一至第三电阻可变元件设置在位线和存取晶体管之间，并且彼此电连接。 第一至第三电流供应线与第一至第三电阻可变元件交替堆叠。 第一至第三电阻可变元件具有相等的电阻。

Patent Agency Ranking