公开(公告)号：US10098243B2

公开(公告)日：2018-10-09

申请号：US14857074

申请日：2015-09-17

Applicant: IBIDEN CO., LTD.

Inventor： Toshiki Furutani ,  Yuki Yoshikawa

IPC: H05K1/14 ,  H05K3/46 ,  H05K1/02 ,  H05K3/34

Abstract: A printed wiring board includes a core laminate body including insulating layers, conductor layers including first and second conductor layers, and via conductors having smaller end surfaces connected to the first conductor layer, a first build-up layer formed on the core body and including an interlayer, a conductor layer on the interlayer, and via conductors having smaller end surfaces connected to the first conductor layer, and a second build-up layer formed on the core body and including an interlayer and a conductor layer on the interlayer. The first conductor layer is embedded such that the first conductor layer has exposed surface on the surface of the core body, the second conductor layer is formed on the other surface of the core body, and the first conductor layer has wiring pattern having the smallest minimum width of wiring patterns of the conductor layers in the core body and build-up layers.

公开(公告)号：US09951434B2

公开(公告)日：2018-04-24

申请号：US14700313

申请日：2015-04-30

Applicant: IBIDEN CO., LTD.

Inventor： Toshiki Furutani ,  Yuki Yoshikawa

IPC: H05K3/46 ,  H05K3/18 ,  H05K1/11 ,  H05K1/02 ,  H05K1/03 ,  C25D5/48 ,  C25D7/12 ,  C25D5/02 ,  C25D7/00 ,  C23C18/16

CPC classification number: C25D5/48 ,  C23C18/1653 ,  C25D5/022 ,  C25D7/00 ,  C25D7/123 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H05K1/0271 ,  H05K1/0298 ,  H05K1/0366 ,  H05K1/115 ,  H05K3/188 ,  H05K3/4617 ,  H05K3/4632 ,  H05K3/4682 ,  H05K2201/0195 ,  H05K2203/0723 ,  H01L2924/00014

Abstract: A printed wiring board includes a core laminate including insulating layers and conductor layers, a first build-up layer formed on first surface of the laminate and including first interlayer resin and conductor layers, and a second build-up layer formed on second surface of the core laminate on the opposite side and including second interlayer resin and conductor layers. The conductor layers in the laminate include first and second conductor layers such that the first conductor layer is embedded in one of the insulating layers forming the first surface of the laminate and has an exposed surface exposed from the insulating layer and that the second conductor layer is formed on one of the insulating layers forming the second surface of the laminate, and the first interlayer resin layer has thickness greater than thickness of the second interlayer resin layer.

公开(公告)号：US09401320B2

公开(公告)日：2016-07-26

申请号：US14638324

申请日：2015-03-04

Applicant: IBIDEN CO., LTD.

Inventor： Tomoya Daizo ,  Takema Adachi ,  Takeshi Furusawa ,  Wataru Nakamura ,  Yuki Ito ,  Yuki Yoshikawa ,  Tomoyoshi Hirabayashi

IPC: H01L23/498 ,  H01L25/10 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L23/49811 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49894 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A combined substrate includes a first substrate having multiple first metal posts, a second substrate having multiple second metal posts such that the second metal posts are positioned to oppose the first metal posts, respectively, and multiple solder structures interposed between the first metal posts and the second metal posts, respectively. The first metal posts and/or the second metal posts have recessed surfaces formed such that the solder structures are formed on the recessed surfaces, respectively.

Abstract translation: 组合衬底包括具有多个第一金属柱的第一衬底，具有多个第二金属柱的第二衬底，使得第二金属柱分别定位成与第一金属柱相对，以及插入在第一金属柱和第二金属柱之间的多个焊料结构 第二金属柱。 第一金属柱和/或第二金属柱具有形成为使得焊料结构分别形成在凹陷表面上的凹陷表面。

公开(公告)号：US10745819B2

公开(公告)日：2020-08-18

申请号：US15958332

申请日：2018-04-20

Applicant: IBIDEN CO., LTD.

Inventor： Toshiki Furutani ,  Yuki Yoshikawa

IPC: H05K3/46 ,  H05K3/18 ,  H05K1/11 ,  H05K1/02 ,  C25D7/12 ,  C25D5/02 ,  C23C18/16 ,  C25D5/48 ,  H05K1/03 ,  C25D7/00

Abstract: A printed wiring board includes a core laminate including insulating layers and conductor layers, a first build-up layer formed on first surface of the laminate and including first interlayer resin and conductor layers, and a second build-up layer formed on second surface of the core laminate on the opposite side and including second interlayer resin and conductor layers. The conductor layers in the laminate include first and second conductor layers such that the first conductor layer is embedded in one of the insulating layers forming the first surface of the laminate and has an exposed surface exposed from the insulating layer and that the second conductor layer is formed on one of the insulating layers forming the second surface of the laminate, and the first interlayer resin layer has thickness greater than thickness of the second interlayer resin layer.

公开(公告)号：US20150255433A1

公开(公告)日：2015-09-10

申请号：US14638324

申请日：2015-03-04

Applicant: IBIDEN CO., LTD.

Inventor： Tomoya DAIZO ,  Takema Adachi ,  Takeshi Furusawa ,  Wataru Nakamura ,  Yuki Ito ,  Yuki Yoshikawa ,  Tomoyoshi Hirabayashi

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L23/49811 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49894 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A combined substrate includes a first substrate having multiple first metal posts, a second substrate having multiple second metal posts such that the second metal posts are positioned to oppose the first metal posts, respectively, and multiple solder structures interposed between the first metal posts and the second metal posts, respectively. The first metal posts and/or the second metal posts have recessed surfaces formed such that the solder structures are formed on the recessed surfaces, respectively.

Abstract translation: 组合衬底包括具有多个第一金属柱的第一衬底，具有多个第二金属柱的第二衬底，使得第二金属柱分别定位成与第一金属柱相对，以及插入在第一金属柱和第二金属柱之间的多个焊料结构 第二金属柱。 第一金属柱和/或第二金属柱具有形成为使得焊料结构分别形成在凹陷表面上的凹陷表面。

公开(公告)号：US09601422B2

公开(公告)日：2017-03-21

申请号：US14721239

申请日：2015-05-26

Applicant: IBIDEN CO., LTD.

Inventor： Toshiki Furutani ,  Yuki Yoshikawa

IPC: H05K7/00 ,  H01L23/498 ,  H01L21/48 ,  H05K1/02 ,  H01L23/00 ,  H05K3/46

CPC classification number: H01L23/49822 ,  H01L21/48 ,  H01L21/4857 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49894 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/0271 ,  H05K3/4682 ,  H05K2201/0191 ,  H05K2201/0209 ,  H01L2224/45099 ,  H01L2224/13099 ,  H01L2924/00012

Abstract: A printed wiring board includes a first interlayer, a first conductive layer on first-surface side of the first interlayer, a second conductive layer on second-surface side of the first interlayer, a first buildup layer including interlayers and conductive layers and formed on first surface of the first interlayer, and a second buildup layer including interlayers and conductive layers and formed on second surface of the first interlayer. The first conductive layer is formed such that the first conductive layer is embedded in the first interlayer and exposing surface on the first surface of the first interlayer, the second conductive layer is formed on the second surface of the first interlayer, and the interlayers in the first buildup layer include a second interlayer positioned adjacent to the first conductive layer and having the greatest thickness among the first interlayer and interlayers in the first and second buildup layers.

公开(公告)号：US20180237934A1

公开(公告)日：2018-08-23

申请号：US15958332

申请日：2018-04-20

Applicant: IBIDEN CO., LTD.

Inventor： Toshiki Furutani ,  Yuki Yoshikawa

IPC: C25D5/48 ,  H05K1/11 ,  H05K1/02 ,  H05K3/18 ,  C25D7/12 ,  H05K3/46 ,  H05K1/03 ,  C23C18/16 ,  C25D7/00 ,  C25D5/02

Abstract: A printed wiring board includes a core laminate including insulating layers and conductor layers, a first build-up layer formed on first surface of the laminate and including first interlayer resin and conductor layers, and a second build-up layer formed on second surface of the core laminate on the opposite side and including second interlayer resin and conductor layers. The conductor layers in the laminate include first and second conductor layers such that the first conductor layer is embedded in one of the insulating layers forming the first surface of the laminate and has an exposed surface exposed from the insulating layer and that the second conductor layer is formed on one of the insulating layers forming the second surface of the laminate, and the first interlayer resin layer has thickness greater than thickness of the second interlayer resin layer.

公开(公告)号：US20160088727A1

公开(公告)日：2016-03-24

申请号：US14857074

申请日：2015-09-17

Applicant: IBIDEN CO., LTD.

Inventor： Toshiki FURUTANI ,  Yuki Yoshikawa

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/18

CPC classification number: H05K3/4673 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H05K1/0271 ,  H05K3/3436 ,  H05K2201/096 ,  H05K2201/09827 ,  H01L2924/00014

Abstract: A printed wiring board includes a core laminate body including insulating layers, conductor layers including first and second conductor layers, and via conductors having smaller end surfaces connected to the first conductor layer, a first build-up layer formed on the core body and including an interlayer, a conductor layer on the interlayer, and via conductors having smaller end surfaces connected to the first conductor layer, and a second build-up layer formed on the core body and including an interlayer and a conductor layer on the interlayer. The first conductor layer is embedded such that the first conductor layer has exposed surface on the surface of the core body, the second conductor layer is formed on the other surface of the core body, and the first conductor layer has wiring pattern having the smallest minimum width of wiring patterns of the conductor layers in the core body and build-up layers.

Abstract translation: 一种印刷电路板，包括具有绝缘层的芯层压体，包括第一和第二导体层的导体层，以及连接到第一导体层的具有较小端面的通孔导体，形成在芯体上的第一堆积层， 中间层，中间层上的导体层和连接到第一导体层的较小端面的通孔导体，以及形成在芯体上并在中间层上包括中间层和导体层的第二堆积层。 第一导体层被嵌入，使得第一导体层在芯体的表面上具有暴露表面，第二导体层形成在芯体的另一个表面上，并且第一导体层具有最小的布线图案 芯体和堆积层中的导体层的布线图形的宽度。