公开(公告)号：US3623923A

公开(公告)日：1971-11-30

申请号：US3623923D

申请日：1968-09-03

Applicant: IBM

Inventor： KENNEDY DAVID P ,  PERRI JOHN A ,  RISEMAN JACOB

IPC: H01L29/73 ,  A47B61/04 ,  H01L21/00 ,  H01L21/22 ,  H01L21/331 ,  H01L27/00 ,  B01J17/00 ,  H01L3/00 ,  H01L7/00

CPC classification number: H01L21/22 ,  A47B61/04 ,  H01L21/00 ,  H01L27/00 ,  Y10S148/035 ,  Y10S148/085 ,  Y10S148/106 ,  Y10S148/15 ,  Y10S148/167

Abstract: PLANAR TRANSISTOR HAVING REDUCED JUNCTION AREA FOR SMALL CAPACITANCE. A THIN LAYER OF SEMICONDUCTOR MATERIAL IS PLACED ON A SUBSTRATE MATERIAL WHICH IS NEARLY IMPENETRABLE BARRIER AGAINST DIFFUSION BY NORMALLY USED IMPURITY ATOMS. THE DEPTH OF THE JUNCTION IS LIMITED TO APPROXIMATELY THE THICKNESS OF THE THIN LAYER OF SEMICONDUCTOR MATERIAL, THUS LIMITING THE JUNCTION AREA AND CAPACTANCE.

公开(公告)号：US3617816A

公开(公告)日：1971-11-02

申请号：US3617816D

申请日：1970-02-02

Applicant: IBM

Inventor： RISEMAN JACOB ,  TOTTA PAUL A

IPC: H01L23/485 ,  H01L23/532 ,  H01L3/00 ,  H01L5/00

CPC classification number: H01L24/02 ,  H01L23/53242 ,  H01L23/53252 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/00

Abstract: A metallurgy interconnection system for semiconductor devices made up of laminar stripes, each having a layer of gold disposed between layers of tantalum.

公开(公告)号：US3559003A

公开(公告)日：1971-01-26

申请号：US3559003D

申请日：1969-01-03

Applicant: IBM

Inventor： BEAUDOUIN PIERRE L ,  GLANG REINHARD ,  RISEMAN JACOB

IPC: H01L29/43 ,  H01L21/00 ,  H01L21/28 ,  H01L23/485 ,  H01L23/522 ,  H01L1/14 ,  H01L5/02

CPC classification number: H01L23/485 ,  H01L21/00 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

Abstract: THE PROCESS FOR MAKING, AND THE STRUCTURE OF, AN INTERCONNECTION AND RESISTOR NETWORK UPON A SEMICONDUCTOR SURFACE. THIS NETWORK INCLUDES OHMIC CONTACTS TO THE SEMICONDUCTOR WHICH COMPRISE THE COMBINATION OF A CR-SIO CERMET MATERIAL HAVING A COPPER CONDUCTOR THEREON. THIS COMBINATION OF MATERIALS IS ALSO UTILIZED FOR INTERCONNECTIONS BETWEEN OHMIC CONTACTS. WHERE A RESISTOR IS DESIRED ALONG A INTERCONNECTION LINE, THE COPPER CONDUCTOR IS REMOVED, CAUSING THE CURRENT, WHEN AN ELECTRIC FIELD IS APPLIED, TO PASS THROUGH THE CERMET MATERIAL WHICH NOW FUNCTIONS AS A RESISTOR.

公开(公告)号：US3893156A

公开(公告)日：1975-07-01

申请号：US37529673

申请日：1973-06-29

Applicant: IBM

Inventor： RISEMAN JACOB

IPC: H01L21/60 ,  H01L23/482 ,  H01L3/00 ,  H01L5/00

CPC classification number: H01L24/73 ,  H01L23/4822 ,  H01L24/11 ,  H01L24/81 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01072 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00

Abstract: A beam-lead integrated circuit chip structure which comprises a semiconductor chip substrate having a passivated planar surface from which active and passive devices in the circuit extend into the substrate. A plurality of peripheral beam-leads interconnected with the chip devices extend beyond the periphery of the chip and a plurality of solder mounds having a lower melting point than said beam-leads extends from the surface of the chip to a point beyond the plane of the beam-leads. This chip structure permits a method of automatic alignment of said plurality of beam-leads with a corresponding plurality of beam-leads on a dielectric substrate which involves placing the chip on the substrate so that said plurality of solder mounds are respectively in registration with a plurality of corresponding solder-wettable land pads on said non-wettable dielectric substrate. The structure is then heated to melt the solder mounds, wetting said land pads and thereby moving the chip so as to bring said beam-leads into registration with a plurality of corresponding land leads.

Abstract translation: 一种束引线集成电路芯片结构，其包括具有钝化平面的半导体芯片衬底，电路中的有源和无源器件从该平面延伸到衬底中。 与芯片器件互连的多个外围光束引线延伸超过芯片的周边，并且具有比所述光束引线更低熔点的多个焊料凹槽从芯片的表面延伸到超过芯片的平面的点 光束引线。

公开(公告)号：US3886025A

公开(公告)日：1975-05-27

申请号：US28361472

申请日：1972-08-24

Applicant: IBM

Inventor： RISEMAN JACOB

IPC: G11B5/133 ,  G11B5/23 ,  C09J5/00 ,  G11B5/42 ,  H01F7/06

CPC classification number: G11B5/133 ,  G11B5/232 ,  Y10T29/49039 ,  Y10T29/49057

Abstract: Ferrite recording head members are coated with a layer of silicon nitride prior to filling the gap between the members with nonmagnetic material. The silicon nitride coating protects the ferrite member from attack by the nonmagnetic material.

Abstract translation: 铁氧体记录头构件在用非磁性材料填充构件之间的间隙之前涂覆有氮化硅层。 氮化硅涂层保护铁氧体元件免受非磁性材料的侵蚀。

公开(公告)号：US3614832A

公开(公告)日：1971-10-26

申请号：US3614832D

申请日：1966-03-09

Applicant: IBM

Inventor： CHANCE DUDLEY A ,  IM SAMUEL S ,  PERRI JOHN A ,  RISEMAN JACOB

IPC: B23K1/005 ,  H01L29/12 ,  H01R12/71 ,  H05K3/30

CPC classification number: B23K1/0056 ,  B23K2201/38 ,  H01L24/24 ,  H01L24/82 ,  H01L29/12 ,  H01L2224/2402 ,  H01L2224/24227 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01043 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  Y10T29/49128 ,  Y10T29/49155 ,  H01L2924/00

Abstract: A PLURALITY OF CONNECTIONS FROM ELECTRICALLY CONDUCTIVE LANDS ON AN INSULATING SUBSTRATE TO THE CONTACTS OF A SOLID STATE DEVICE ARE FORMED IN ONE OPERATION BY FIXEDLY POSITIONING THE DEVICE ON, OR IN A CAVITY WITHIN, THE SUBSTRATE. A DECAL, INCLUDING A BACKING PLATE WITH A PLURALITY OF CONDUCTIVE STRIPS WHICH CAN BE ADHERED TO THE PLATE BY MEANS OF A SOLUBLE ADHESIVE, IS POSITIONED OVER THE DEVICE BEARING SUBSTRATE WITH THE STRIPS IN REGISTRY WITH RESPECTIVE CONTACTS AND LANDS. THE STRIPS ARE BROUGHT INTO CONTACT WITH RESPECTIVE CONTACT AND LAND SURFACE PORTIONS AND SUBJECTED TO HEAT AND PRESSURE SUFFICIENT TO CAUSE BONDING THEREBETWEEN. THEREAFTER, THE DECAL BACKING PLATE MAY BE REMOVED FROM THE STRIPS, AS BY DISSOLVING THE ADHESIVE, LEAVING THE STRIPS FIRMLY BONDED TO THE CONTACTS AND LANDS AND BRIDGING THE SPACE THEREBETWEEN, WHEREBY THE LANDS ARE CONNECTED TO THE CONTACTS THROUGH THE STRIPS.

公开(公告)号：US3574680A

公开(公告)日：1971-04-13

申请号：US3574680D

申请日：1968-05-07

Applicant: IBM

Inventor： PERRI JOHN A ,  RISEMAN JACOB

IPC: A63H18/08 ,  C23C14/00 ,  C23C16/00 ,  H01H11/04 ,  H01L21/00 ,  H01L21/24 ,  H01L21/28 ,  H01L21/283 ,  H01L21/285 ,  C23C11/02 ,  H01K7/00

CPC classification number: H01L21/283 ,  C23C14/00 ,  C23C16/00 ,  H01H11/04 ,  H01L21/00 ,  H01L21/24 ,  H01L21/28 ,  H01L21/285 ,  Y10T428/24917

Abstract: A METHOD OF FORMING AN OHMIC CONTACT UPON AN AREA TO BE CONTACTED UPON A SUBSTRATE, SUCH AS AN ACTIVE AREA UPON A SEMICONDUCTOR DEVICE, COMPRISING THE STEPS OF DEPOSITING FROM THE VAPOR PHASE A METAL TO BE DEPOSITED, WHILE SAID AREA IS MAINTAINED AT A FIRST TEMPERATURE AT WHICH GOOD ADHESION BETWEEN SAID AREA AND SAID METAL OCCURS; THEN COMPLETING THE DEPOSITION AT A SECOND LOWER TEMPERATURE, FOR A TIME DURING WHICH NO CONTACT-IMPAIRING REACTIONS MAY OCCUR BETWEEN SAID METAL AND SAID AREA; THEN COOLING THE AREA. EXAMPLES OF GIVEN MATERIALS AND TEMPERATURES ARE INCLUDED.

公开(公告)号：US3546013A

公开(公告)日：1970-12-08

申请号：US3546013D

申请日：1968-09-18

Applicant: IBM

Inventor： PERRI JOHN A ,  RISEMAN JACOB

IPC: C23C8/80 ,  H01L23/29 ,  H01L23/31 ,  H01L23/485 ,  C23B5/50

CPC classification number: H01L23/3157 ,  C23C8/80 ,  H01L23/291 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：US3449049A

公开(公告)日：1969-06-10

申请号：US3449049D

申请日：1966-01-14

Applicant: IBM

Inventor： HARDING WILLIAM E ,  PERRI JOHN A ,  RISEMAN JACOB ,  RUDER WINFIELD S

IPC: G03B27/32 ,  G03B19/02 ,  G03F7/20 ,  H01L21/027 ,  H01L21/30 ,  G03B27/42

CPC classification number: G03F7/70475 ,  G03B19/023