公开(公告)号：US20230162648A1

公开(公告)日：2023-05-25

申请号：US17912985

申请日：2021-02-25

Applicant: IIX INC.

Inventor： Makoto HATAKENAKA ,  Takashi SAKAMOTO ,  Yoshihide MINEGISHI ,  Ryohei HATTA ,  Norimasa SENDA

IPC: G09G3/20

CPC classification number: G09G3/2074 ,  G09G2330/021 ,  G09G2310/08 ,  G09G2300/0452

Abstract: An input signal correction device includes an input circuit, extension circuit, degenerate circuit, separation circuit, recovery circuit and delay adjustment circuit that operate at an operating frequency f, demura circuit that operates at an operating frequency f/2, and adder circuit. The extension circuit extends the period of R and B input signals by a factor of 2 and outputs preprocessing signals, the degenerate circuit degenerates a G input signal, the demura circuit corrects preprocessing signals from the extension and degenerate circuits and outputs correction signals, the separation circuit reduces the period of the R and B correction signals to ½ and outputs differential signals, recovery circuit reduces the period of G correction signal to ½ and outputs the same differential signal over two periods, the delay adjustment circuit delays the input and output signals, and the adder circuit adds the differential signals to the delay signals and outputs output signals.

公开(公告)号：US20230395038A1

公开(公告)日：2023-12-07

申请号：US18028370

申请日：2021-02-25

Applicant: IIX INC.

Inventor： Makoto HATAKENAKA ,  Takashi SAKAMOTO ,  Yoshihide MINEGISHI ,  Ryohei HATTA ,  Norimasa SENDA

IPC: G09G5/04

CPC classification number: G09G5/04 ,  G09G2300/0452 ,  G09G2330/08 ,  G09G2330/10

Abstract: An input signal correction device for reducing power consumption is compatible with a variety of display panels, and includes an input circuit, extension/degeneration circuit, separation/recovery circuit and delay adjustment circuit operating at frequency f, demura circuit operating at frequency f/2, and adder circuit. The extension/degeneration circuit outputs a preprocessing signal increasing the input signal cycle length by 2 or outputs by degenerating the input signal to ½, based on a control signal, the demura circuit outputs a correction signal correcting the preprocessing signal from the extension/degeneration circuit, the separation/recovery circuit outputs a differential signal reducing the correction signal cycle length to ½ or reduces cycle length to ½ and outputs the same differential signal over two cycles, based on a control signal, the delay adjustment circuit outputs a delay signal delaying the input signal, and the adder circuit outputs a signal adding the differential signal to the delay signal.