公开(公告)号：US20170221857A1

公开(公告)日：2017-08-03

申请号：US15422674

申请日：2017-02-02

Applicant: Infineon Technologies AG

Inventor： Joachim MAHLER ,  Edward FUERGUT ,  Georg MEYER-BERG

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/495 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L21/78

CPC classification number: H01L24/96 ,  H01L21/4825 ,  H01L21/4853 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3157 ,  H01L23/49562 ,  H01L23/49844 ,  H01L24/27 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/32225 ,  H01L2224/3224 ,  H01L2224/32245 ,  H01L2224/3226 ,  H01L2224/48225 ,  H01L2224/48245 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/9222 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/83 ,  H01L2224/85399

Abstract: A method of manufacturing a package which comprises encapsulating at least part of an electronic chip by an encapsulant, subsequently covering a part of the electronic chip with a chip attach medium, and attaching the encapsulated electronic chip on a chip carrier via the chip attach medium.

公开(公告)号：US20140117531A1

公开(公告)日：2014-05-01

申请号：US13664418

申请日：2012-10-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Joachim MAHLER ,  Edward FUERGUT ,  Khalil HOSSEINI ,  Georg MEYER-BERG

IPC: H01L23/29 ,  H01L21/56

CPC classification number: H01L23/291 ,  H01L21/561 ,  H01L21/568 ,  H01L23/296 ,  H01L23/562 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Described are techniques related to semiconductor devices that make use of encapsulant. In one implementation, a semiconductor device may be manufactured to include at least an encapsulant that includes at least glass particles.

Abstract translation: 描述了与使用密封剂的半导体器件有关的技术。 在一个实施方案中，可以制造半导体器件以至少包括至少包括玻璃颗粒的密封剂。

公开(公告)号：US20180158759A1

公开(公告)日：2018-06-07

申请号：US15883151

申请日：2018-01-30

Applicant: Infineon Technologies AG

Inventor： Georg MEYER-BERG

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065 ,  H01L21/48 ,  H01L23/31

CPC classification number: H01L23/49513 ,  H01L21/4821 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49541 ,  H01L23/49575 ,  H01L23/49582 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/32 ,  H01L24/82 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/24155 ,  H01L2224/29082 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29155 ,  H01L2224/29164 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/82007 ,  H01L2924/01028 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/06 ,  H01L2924/0665 ,  H01L2924/07025 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/1715 ,  H01L2924/17738 ,  H01L2924/17747 ,  H01L2924/1776 ,  H01L2924/17763 ,  H01L2924/181 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2924/20642 ,  H01L2924/20643 ,  H01L2924/20644 ,  H01L2924/20645 ,  H01L2924/20646 ,  H01L2924/20647 ,  H01L2924/20648 ,  H01L2924/20649 ,  H01L2924/2065 ,  H01L2924/00

Abstract: Various embodiments provide for a chip package including a carrier; a layer over the carrier; a further carrier material over the layer, the further carrier material comprising a foil; one or more openings in the further carrier material, wherein the one or more openings expose at least one or more portions of the layer from the further carrier material; and a chip comprising one or more contact pads, wherein the chip is adhered to the carrier via the one or more exposed portions of the layer.

公开(公告)号：US20150115442A1

公开(公告)日：2015-04-30

申请号：US14068170

申请日：2013-10-31

Applicant: Infineon Technologies AG

Inventor： Georg MEYER-BERG ,  Reinhard Pufall

IPC: H01L23/00

CPC classification number: H01L24/06 ,  H01L24/03 ,  H01L24/14 ,  H01L24/19 ,  H01L24/20 ,  H01L24/81 ,  H01L2224/02317 ,  H01L2224/02373 ,  H01L2224/0401 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00

Abstract: A redistribution layer for a chip is provided, wherein the redistribution layer comprises at least one electrical conductor path connecting two connection points with each other, wherein the at least one electrical conductor path is arranged on a planar supporting layer and wherein the electrical conductor path comprises copper and at least one other further electrical conductive material in an amount of more than 0.04 mass percent.

Abstract translation: 提供了一种用于芯片的再分配层，其中再分配层包括将两个连接点彼此连接的至少一个电导体路径，其中至少一个电导体路径被布置在平面支撑层上，并且其中电导体路径包括 铜和至少一种其它导电材料，其量大于0.04质量％。