公开(公告)号：US20230017307A1

公开(公告)日：2023-01-19

申请号：US17377486

申请日：2021-07-16

Applicant: Infineon Technologies AG

Inventor： Carmelo Giunta ,  Marcus Nuebling ,  Steffen Thiele

IPC: G01R31/52 ,  H03K17/687 ,  G01R31/26

Abstract: A driver device includes: a voltage terminal; a ground terminal; an output terminal; a first nMOS power transistor having a drain electrically connected to the voltage terminal, a source electrically connected to the output terminal, and a gate; an overvoltage protection circuit configured to limit a gate-to-source voltage of the first nMOS power transistor in a normal operating mode for the driver device; a pulldown circuit configured to force the first nMOS power transistor off in a stress test mode for the driver device; and a blocking circuit configured to block current flow from the output terminal to the ground terminal through the overvoltage protection circuit and the pulldown circuit in the stress test mode. A method of stress testing the driver device is also described.

公开(公告)号：US20170257025A1

公开(公告)日：2017-09-07

申请号：US15060737

申请日：2016-03-04

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Steffen Thiele

IPC: H02M3/156 ,  H01L29/78 ,  H01L29/40 ,  H01L29/10 ,  H01L29/06

CPC classification number: H02M3/156 ,  H01L29/063 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/7825 ,  H01L29/7831 ,  H02M3/155

Abstract: A switched-mode power converter includes an inductive storage element and a cascode circuit. The cascode circuit includes a double-gate field effect transistor. A switchable load path of the double-gate field effect transistor is electrically connected in series with the inductive storage element.

公开(公告)号：US09488674B2

公开(公告)日：2016-11-08

申请号：US14326483

申请日：2014-07-09

Applicant: Infineon Technologies AG

Inventor： Carlos Marques Martins ,  Steffen Thiele ,  Aron Theil

IPC: G01R1/04

CPC classification number: G01R1/0416 ,  G01R31/31905

Abstract: A testing device in accordance with various embodiments may include: a plurality of first terminals configured to be connected to a plurality of devices-under-test, wherein each first terminal of the plurality of first terminals may be configured to be connected to a respective device-under-test of the plurality of devices-under-test; a signal interface configured to be connected to a tester; and a circuit configured to exchange an identical first signal with each device-under-test of the plurality of devices-under-test through a respective first terminal of the plurality of first terminals, and to exchange at least one interface signal with the tester through the signal interface.

Abstract translation: 根据各种实施例的测试装置可以包括：多个第一端子，被配置为连接到被测试的多个器件，其中多个第一端子中的每个第一端子可以被配置为连接到相应的器件 对被测试的多个设备进行测试; 被配置为连接到测试器的信号接口; 以及电路，被配置为通过所述多个第一终端中的相应的第一终端与被测试的所述多个被测器件中的每个被测器件交换相同的第一信号，并且与所述测试器交换至少一个接口信号 信号接口。

公开(公告)号：US20160164279A1

公开(公告)日：2016-06-09

申请号：US14564172

申请日：2014-12-09

Applicant: Infineon Technologies AG

Inventor： Michael Asam ,  Andreas Meiser ,  Steffen Thiele

IPC: H02H9/02 ,  G01R19/165 ,  H03K19/0185

CPC classification number: G01R19/16519 ,  G01R19/16538 ,  H02H3/087 ,  H03K19/018507

Abstract: Circuits, switches with over-current protection and methods for measuring a current are described herein. A circuit configured to provide a current from a supply voltage to a load includes a first transistor, a second transistor, and a detecting circuit. The first transistor has a larger active area than the second transistor. The detecting circuit is configured to detect a current through the second transistor. A same voltage is applied between a control terminal of the first transistor and a first controlled terminal of the first transistor and is applied between a control terminal of the second transistor and a first controlled terminal of the second transistor. The detecting circuit is coupled to the second controlled terminal of the second transistor and is coupled to the supply voltage.

Abstract translation: 这里描述了具有过电流保护的电路，开关和用于测量电流的方法。 配置成将电流从电源电压提供给负载的电路包括第一晶体管，第二晶体管和检测电路。 第一晶体管具有比第二晶体管更大的有源面积。 检测电路被配置为检测通过第二晶体管的电流。 在第一晶体管的控制端子和第一晶体管的第一受控端子之间施加相同的电压，并施加在第二晶体管的控制端子和第二晶体管的第一受控端子之间。 检测电路耦合到第二晶体管的第二受控端并耦合到电源电压。

公开(公告)号：US20150145538A1

公开(公告)日：2015-05-28

申请号：US14091474

申请日：2013-11-27

Applicant: Infineon Technologies AG

Inventor： Steffen Thiele

IPC: G01R19/00 ,  H01C7/10

CPC classification number: G01R19/32 ,  G01R1/203

Abstract: A circuit is provided, including a first resistor, a second resistor and a control unit. The second resistor may have an adjustable resistance. The control unit may be configured to adjust the second resistor to have a first resistance at which a voltage due to a first current flowing through the first resistor is equal to a voltage due to a second current flowing through the second resistor. The control unit may be further configured to adjust the second resistor to have a second resistance at which a voltage due to another first current different from the first current and flowing through the first resistor is equal to the voltage due to the second current flowing through the second resistor. The control unit may be still further configured to adjust the second resistor to have a third resistance based on at least a difference of the first resistance and the second resistance.

Abstract translation: 提供一种电路，包括第一电阻器，第二电阻器和控制单元。 第二电阻器可以具有可调电阻。 控制单元可以被配置为将第二电阻器调整为具有第一电阻，在该第一电阻处，由于流过第一电阻器的第一电流引起的电压等于由于流过第二电阻器的第二电流而导致的电压。 控制单元还可以被配置为将第二电阻器调整为具有第二电阻，在该第二电阻处，由于与第一电流不同的第一电流产生的电流并且流过第一电阻器的电压等于由于第二电流流过第一电流而导致的电压 第二电阻。 控制单元还可以被配置为基于至少第一电阻和第二电阻的差异来调整第二电阻器以具有第三电阻。

公开(公告)号：US10950509B2

公开(公告)日：2021-03-16

申请号：US16399603

申请日：2019-04-30

Applicant: Infineon Technologies AG

Inventor： Rainald Sander ,  Thomas Bemmerl ,  Steffen Thiele

IPC: H01L27/092 ,  H01L29/06 ,  H01L21/66 ,  H01L23/495 ,  H01L21/48

Abstract: A semiconductor device includes a first chip pad, a power semiconductor chip arranged on the first chip pad and including at least a first and a second power electrode, and a clip connected to the first power electrode. In this case, an integral part of the clip forms a shunt resistor and a first contact finger of the shunt resistor is embodied integrally with the clip.

公开(公告)号：US10451669B2

公开(公告)日：2019-10-22

申请号：US15720250

申请日：2017-09-29

Applicant: Infineon Technologies AG

Inventor： Carlos Joao Marques Martins ,  Aron Theil ,  Steffen Thiele

IPC: G01R31/28 ,  H01L29/78 ,  G01R31/26 ,  G01R31/02

Abstract: Disclosed is a method, a circuit arrangement, and an electronic circuit. The method includes discharging a gate-source capacitance of a transistor device from a first voltage level to a second voltage level with a first resistor connected in parallel with the gate-source capacitance and measuring a first discharging time associated with the discharging, and discharging the gate-source capacitance from the first voltage level to the second voltage level with the first resistor and a second resistor connected in parallel with the gate-source capacitance and measuring a second discharging time associated with the discharging. The method further includes comparing a ratio between the first discharging time and the second discharging time with a predefined threshold, and detecting a fault based on the comparing.

公开(公告)号：US20160011232A1

公开(公告)日：2016-01-14

申请号：US14326483

申请日：2014-07-09

Applicant: Infineon Technologies AG

Inventor： Carlos Marques Martins ,  Steffen Thiele ,  Aron Theil

IPC: G01R1/04

CPC classification number: G01R1/0416 ,  G01R31/31905

Abstract: A testing device in accordance with various embodiments may include: a plurality of first terminals configured to be connected to a plurality of devices-under-test, wherein each first terminal of the plurality of first terminals may be configured to be connected to a respective device-under-test of the plurality of devices-under-test; a signal interface configured to be connected to a tester; and a circuit configured to exchange an identical first signal with each device-under-test of the plurality of devices-under-test through a respective first terminal of the plurality of first terminals, and to exchange at least one interface signal with the tester through the signal interface.

Abstract translation: 根据各种实施例的测试装置可以包括：多个第一端子，被配置为连接到被测试的多个器件，其中多个第一端子中的每个第一端子可以被配置为连接到相应的器件 对被测试的多个设备进行测试; 被配置为连接到测试器的信号接口; 以及电路，被配置为通过所述多个第一终端中的相应的第一终端与被测试的所述多个被测器件中的每个被测器件交换相同的第一信号，并且与所述测试器交换至少一个接口信号 信号接口。

公开(公告)号：US11549998B1

公开(公告)日：2023-01-10

申请号：US17377486

申请日：2021-07-16

Applicant: Infineon Technologies AG

Inventor： Carmelo Giunta ,  Marcus Nuebling ,  Steffen Thiele

IPC: G01R31/52 ,  G01R31/26 ,  H03K17/687

Abstract: A driver device includes: a voltage terminal; a ground terminal; an output terminal; a first nMOS power transistor having a drain electrically connected to the voltage terminal, a source electrically connected to the output terminal, and a gate; an overvoltage protection circuit configured to limit a gate-to-source voltage of the first nMOS power transistor in a normal operating mode for the driver device; a pulldown circuit configured to force the first nMOS power transistor off in a stress test mode for the driver device; and a blocking circuit configured to block current flow from the output terminal to the ground terminal through the overvoltage protection circuit and the pulldown circuit in the stress test mode. A method of stress testing the driver device is also described.

公开(公告)号：US10128750B2

公开(公告)日：2018-11-13

申请号：US15060737

申请日：2016-03-04

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Steffen Thiele

IPC: H02M3/156 ,  H01L29/10 ,  H01L29/06 ,  H01L29/40 ,  H01L29/78

Abstract: A switched-mode power converter includes an inductive storage element and a cascode circuit. The cascode circuit includes a double-gate field effect transistor. A switchable load path of the double-gate field effect transistor is electrically connected in series with the inductive storage element.