公开(公告)号：US11024708B1

公开(公告)日：2021-06-01

申请号：US16824761

申请日：2020-03-20

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Yongliang Li ,  Xiaohong Cheng ,  Qingzhu Zhang ,  Huaxiang Yin ,  Wenwu Wang

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/417 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/088

Abstract: A semiconductor device, including: a silicon substrate; multiple fin structures, formed on the silicon substrate, where each extends along a first direction; a shallow trench insulator, located among the multiple fin structures; a gate stack, intersecting with the multiple fin structures and extending along a second direction, where first spacers are formed on two sidewalls in the first direction of the gate stack; source-or-drain regions, formed on the multiple fin structures, and located at two sides of the gate stack along the first direction; and a channel region, including a portion of the multiple fin structures located between the first spacers. and notch structures. A notch structure recessed inward is located between each of the multiple fin structures and the silicon substrate. The notch structure includes an isolator that isolates each of the multiple fin structures from the silicon substrate.

公开(公告)号：US20230261050A1

公开(公告)日：2023-08-17

申请号：US18059960

申请日：2022-11-29

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Yongliang Li ,  Xiaohong Cheng ,  Fei Zhao ,  Jun Luo ,  Wenwu Wang

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78

CPC classification number: H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/6681 ,  H01L29/7831 ,  H01L29/785

Abstract: A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes: a substrate and a channel portion. The channel portion includes a first portion including a fin-shaped structure protruding with respect to the substrate and a second portion located above the first portion and spaced apart from the first portion. The second portion includes one or more nanowires or nanosheets spaced apart from each other. Source/drain portions are arranged on two opposite sides of the channel portion in a first direction and in contact with the channel portion. A gate stack extends on the substrate in a second direction intersecting with the first direction, so as to intersect with the channel portion.

公开(公告)号：US11476328B2

公开(公告)日：2022-10-18

申请号：US16824810

申请日：2020-03-20

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Yongliang Li ,  Xiaohong Cheng ,  Qingzhu Zhang ,  Huaxiang Yin ,  Wenwu Wang

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/84

Abstract: A stacked nanowire or nanosheet gate-all-around device, including: a silicon substrate; stacked nanowires or nanosheets located on the silicon substrate, extending along a first direction gate stacks and including multiple nanowires or nanosheets that are stacked; a gate stack, surrounding each of the stacked nanowires or nanosheets, and extending along a second direction, where first spacers are located on two sidewalls of the gate stack in the first direction; source-or-drain regions, located at two sides of the gate stack along the first direction; a channel region, including a portion of the stacked nanowires or nanosheets that is located between the first spacers. A notch structure recessed inward is located between the stacked nanowires or nanosheets and the silicon substrate, and includes an isolator that isolates the stacked nanowires or nanosheets from the silicon substrate. A method for manufacturing the stacked nanowire or nanosheet gate-all-around device is further provided.

公开(公告)号：US20250015084A1

公开(公告)日：2025-01-09

申请号：US18763440

申请日：2024-07-03

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Yongliang Li ,  Fei Zhao

IPC: H01L27/092 ,  H01L21/225 ,  H01L21/762 ,  H01L29/06 ,  H01L29/161 ,  H01L29/24 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device and a method for manufacturing the same. The semiconductor device comprises an n-channel GAA transistor and a p-channel GAA transistor, which are spaced apart. Each of the n-channel GAA transistor and the p-channel GAA transistor comprises a source, a drain, and at least one nanostructure layer located between the source and the drain. The p-channel GAA transistor further comprises a gate stack structure and a gate sidewall. In the p-channel GAA transistor, the at least one nanostructure layer comprises a channel portion that is covered by the gate stack structure and a connecting portion that is covered by the gate sidewall, and germanium content in the channel portion is greater than germanium content in the connecting portion and is greater than germanium content in the at least one nanostructure layer of the n-channel GAA transistor.

公开(公告)号：US20230326965A1

公开(公告)日：2023-10-12

申请号：US18087347

申请日：2022-12-22

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Yongliang Li ,  Anlan Chen ,  Fei Zhao ,  Xiaohong Cheng ,  Huaxiang Yin ,  Jun Luo ,  Wenwu Wang

IPC: H01L29/786 ,  H01L29/775 ,  H01L29/66 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device and a method for manufacturing the same. The semiconductor device includes: a first gate-all-around (GAA) transistor disposed in the first region, including a first nanowire or nanosheet of at least one first layer, the at least one first layer and the substrate form a first group, among which all pairs of adjacent layers are separated by first distances, respectively; and a second GAA transistor disposed in the second region, including a second nanowire or nanosheet of at least two second layers, the at least two second layers and the substrate form a second group, among which the second layers are separated by second distances, respectively; where a minimum first distance is greater than a maximum second distance, and a quantity of the at least one first layer is less than a quantity of the at least two second layers.

公开(公告)号：US20200381540A1

公开(公告)日：2020-12-03

申请号：US16845351

申请日：2020-04-10

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Yongliang Li ,  Anyan Du ,  Zhenhua Wu ,  Chaolei Li ,  Wenwu Wang

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L21/8234

Abstract: The disclosure provides a semiconductor device, a manufacturing method thereof, and an electronic device including the device. The semiconductor device includes: a substrate, the substrate being a silicon substrate or an SOI substrate; a SiGe Fin formed on the substrate, wherein the SiGe Fin is a sandwich-like SixGe1-x/SiyGe1-y/SizGe1-z structure with different Ge contents in the horizontal direction, where x is 0.05˜0.95, y is 0.1˜0.9, and z is 0.05˜0.95; and a shallow trench isolation region disposed on the substrate and adjacent to all sides of the SiGe Fin, wherein a top surface of the SiGe Fin facing away from the substrate protrudes from the shallow trench isolation region. The disclosure proposes a device structure of a sandwich-like SixGe1-x/SiyGe1-y/SizGe1-z Fin structure with different Ge contents, which can adjust the Ge content to change the band gap, thereby adjusting the threshold, and improving electrical properties such as mobility (effective mass change) and leakage. The disclosure can be applied to devices such as FinFETs or vertical nanowires.

公开(公告)号：US20240213336A1

公开(公告)日：2024-06-27

申请号：US18522198

申请日：2023-11-28

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Yongliang Li ,  Fei Zhao

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/41733 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775

Abstract: A gate-all-around transistor is provided, including: a semiconductor substrate, a nanostructure, a gate stack structure and a gate length defining structure. In a length direction of the nanostructure, each layer of nanostructure includes a source region, a drain region, and a channel region between the two. Materials of the source region and drain region include a first metal semiconductor compound. The gate stack structure surrounds the channel region. In a length direction of the gate stack structure, a sidewall of the gate stack structure is recessed relative to a sidewall of the channel region to form a recess, and the gate length defining structure is filled in the recess. The gate length defining structure is made of a second metal semiconductor compound, and a semiconductor material for making the second metal semiconductor compound is different from that for making the first metal semiconductor compound.

公开(公告)号：US20250089305A1

公开(公告)日：2025-03-13

申请号：US18817680

申请日：2024-08-28

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Yongliang Li ,  Huaizhi Luo ,  Jun Luo ,  Wenwu Wang

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/16 ,  H01L29/165 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A gate-all-around transistor and a method for manufacturing the same. The gate-all-around transistor comprises: a semiconductor substrate; a source, a drain, and at least one nanostructure layer, which are disposed on the semiconductor substrate; and a gate stack structure surrounding each nanostructure layer, where the at least one nanostructure layer is disposed between the source and the drain, each nanostructure layer comprises a first material layer and second material layers, the second material layers are disposed at two sides of the first material layer along a thickness direction of the first material layer, each of the first material layer and the second material layers is in contact with both the source and the drain, and at least a part of the second material layers is different from the first material layer in material.