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1.发明申请SYSTEM FOR ELECTRICAL TESTING AND MANUFACTURING OF A 3-D CHIP STACK AND METHOD 有权一种三维芯片堆栈和方法的电气测试和制造系统公开(公告)号：US20140300382A1
公开(公告)日：2014-10-09
申请号：US14082528
申请日：2013-11-18
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Martin ECKERT , Eckhard KUNIGKEIT , Otto A. TORREITER , Quintino L. TRIANNI
IPC: G01R31/28
CPC classification number: G01R31/2886 , G01R31/2896 , H01L22/14 , H01L23/3128 , H01L23/49811 , H01L23/49816 , H01L25/0652 , H01L25/0657 , H01L2224/13 , H05K3/325 , H05K3/341 , Y10T29/49004 , Y10T29/4913 , Y10T29/49149
Abstract: A method for electrical testing of a 3-D integrated circuit chip stack is described. The 3-D integrated circuit chip stack comprises at least a first integrated circuit chip and a second integrated circuit chip. The first integrated circuit chip and the second integrated circuit chip are not soldered together for performing electrical testing.
Abstract translation: 描述了一种用于3-D集成电路芯片堆栈的电测试的方法。 3-D集成电路芯片堆叠至少包括第一集成电路芯片和第二集成电路芯片。 第一集成电路芯片和第二集成电路芯片不被焊接在一起用于进行电气测试。
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公开(公告)号：US20170108547A1
公开(公告)日：2017-04-20
申请号：US15176681
申请日：2016-06-08
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Joerg G. APPINGER , Eberhard DENGLER , Roland DIETERLE , Martin ECKERT , Gabriele KUCZERA , Siegfried TOMASCHKO , Otto TORREITER , Quintino Lorenzo TRIANNI
CPC classification number: G01R1/06794 , G01R1/07307 , G01R31/2887 , G01R31/2891
Abstract: A wafer probe alignment system and method for aligning a probe to a chip wafer for testing a chip on the wafer are provided. At least two corners of the probe are adjustable in a same direction in relation to a primary corner of the probe. The alignment approach includes providing a grid of signal pins for corresponding contact pads of the chip under test, determining for each signal pin whether an electrical contact is established to a corresponding contact pad of the chip under contact force, and adjusting a position of each of the at least two corners by a corner individual delta position value with respect to the direction depending on a result of the determining in order to establish an electrical contact between each of the pins and the corresponding contact pads of the chip under test.
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Patent Agency Ranking
公开(公告)号：US20170108534A1
公开(公告)日：2017-04-20
申请号：US14887510
申请日：2015-10-20
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Joerg G. APPINGER , Eberhard DENGLER , Roland DIETERLE , Martin ECKERT , Gabriele KUCZERA , Siegfried TOMASCHKO , Otto TORREITER , Quintino Lorenzo TRIANNI
CPC classification number: G01R1/06794 , G01R1/07307 , G01R31/2887 , G01R31/2891
Abstract: A water probe alignment system and method for aligning a probe to a chip wafer for testing a chip on the wafer are provided. At least two corners of the probe are adjustable in a same direction in relation to a primary corner of the probe. The alignment approach includes providing a grid of signal pins for corresponding contact pads of the chip under test, determining for each signal pin whether an electrical contact is established to a corresponding contact pad of the chip under contact force, and adjusting a position of each of the at least two corners by a corner individual delta position value with respect to the direction depending on a result of the determining in order to establish an electrical contact between each of the pins and the corresponding contact pads of the chip under test.
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公开(公告)号：US20180204618A1
公开(公告)日：2018-07-19
申请号：US15834221
申请日：2017-12-07
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Martin ECKERT , Alexander FRITSCH
IPC: G11C15/04
CPC classification number: G11C15/04 , G11C29/26 , G11C29/34 , G11C29/38 , G11C29/44 , G11C2029/1804
Abstract: A logic circuit is provided including at least two input cells and a sense circuit. The input cells are connected to a common result line. Further, the input cells are operable for influencing an electrical quantity at the result line. The sense circuit is connected to the result line, and is adapted to output a discrete value out of more than two possible values based on the electrical quantity.
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公开(公告)号：US20140316725A1
公开(公告)日：2014-10-23
申请号：US14246376
申请日：2014-04-07
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Martin ECKERT , Hubert HARRER , Thomas STRACH
IPC: G01R31/40
Abstract: A method is provided for determining a power noise histogram of a computer system. The computer system includes a skitter circuit with multiple skitter bins, each skitter bin of the multiple skitter bins being connected to a signal line at one or more clock cycles. The method includes: connecting each skitter bin to an individual counter circuit; and incrementing a counter when the respective skitter bin is enabled.
Abstract translation: 提供了一种用于确定计算机系统的功率噪声直方图的方法。 计算机系统包括具有多个切分机箱的分切机电路，多个分频器机箱的每个切换机箱以一个或多个时钟周期连接到信号线。 该方法包括：将每个小节仓连接到单独的计数器电路; 并且当相应的扫描槽被启用时递增一个计数器。
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公开(公告)号：US20190206492A1
公开(公告)日：2019-07-04
申请号：US16296356
申请日：2019-03-08
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Martin ECKERT , Alexander FRITSCH
CPC classification number: G11C15/04 , G11C29/26 , G11C29/34 , G11C29/38 , G11C29/44 , G11C2029/1804
Abstract: A logic circuit is provided including at least two input cells and a sense circuit. The input cells are connected to a common result line. Further, the input cells are operable for influencing an electrical quantity at the result line. The sense circuit is connected to the result line, and is adapted to output a discrete value out of more than two possible values based on the electrical quantity.
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7.发明申请SYSTEM FOR ELECTRICAL TESTING AND MANUFACTURING OF A 3-D CHIP STACK AND METHOD 审中-公开一种三维芯片堆栈和方法的电气测试和制造系统公开(公告)号：US20160097807A1
公开(公告)日：2016-04-07
申请号：US14965163
申请日：2015-12-10
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Martin ECKERT , Eckhard KUNIGKEIT , Otto A. TORREITER , Quintino L. TRIANNI
IPC: G01R31/28
CPC classification number: G01R31/2886 , G01R31/2896 , H01L22/14 , H01L23/3128 , H01L23/49811 , H01L23/49816 , H01L25/0652 , H01L25/0657 , H01L2224/13 , H05K3/325 , H05K3/341 , Y10T29/49004 , Y10T29/4913 , Y10T29/49149
Abstract: A method for electrical testing of a 3-D integrated circuit chip stack is described. The 3-D integrated circuit chip stack comprises at least a first integrated circuit chip and a second integrated circuit chip. The first integrated circuit chip and the second integrated circuit chip are not soldered together for performing electrical testing.
Abstract translation: 描述了一种用于3-D集成电路芯片堆栈的电测试的方法。 3-D集成电路芯片堆叠至少包括第一集成电路芯片和第二集成电路芯片。 第一集成电路芯片和第二集成电路芯片不被焊接在一起用于进行电气测试。
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