SINGLE FLUX QUANTUM CIRCUITRY FOR QUANTIZED FLUX BIAS CONTROL

    公开(公告)号:US20240334844A1

    公开(公告)日:2024-10-03

    申请号:US18128447

    申请日:2023-03-30

    CPC classification number: H10N60/12 G06N10/40 H03K19/195 H10N60/805

    Abstract: A system comprises a superconducting quantizing inductor and superconducting control circuitry, which is coupled to the superconducting quantizing inductor to form a superconducting loop, and which is configured to selectively inject a quantized amount of positive or negative current into the superconducting loop to generate a quantized circulating current in the superconducting loop. The quantized circulating current comprises a time-varying or static circulating current. The superconducting control circuitry comprises first and second current generator circuits which comprise a first and second plurality of Josephson junctions, respectively, which are configured to inject quantized amounts of positive current and negative current into the superconducting loop in response to single flux quantum pulses. The first and second current generator circuits comprise respective first and second current distribution networks that are configured to distribute circulating current in the superconducting loop to the respective Josephson junctions without causing switching of the Josephson junctions.

    JOSEPHSON RF ENVELOPE-TO-DC CONVERTER
    2.
    发明公开

    公开(公告)号:US20240030912A1

    公开(公告)日:2024-01-25

    申请号:US17871933

    申请日:2022-07-23

    Inventor: Matthew Beck

    CPC classification number: H03K17/92 H03K3/01

    Abstract: A method of using Josephson Junctions to convert the envelope of radio-frequency signals into baseband control pulses includes injecting a biasing current into an envelope detector circuit. The biasing current is identified based on first and second critical currents of superconducting devices in the envelope detector circuit. The first critical current corresponds to the envelope detector circuit receiving no RF signals. The second critical current corresponds to the envelope detector circuit receiving maximum RF signals. The method further includes receiving a modulated radio frequency (RF) signal at the envelope detector circuit to detect an envelope of the received RF signal. The output of the envelope detector circuit is used to drive an output load. The output is generated based on the detected envelope by the envelope detector circuit.

    RADIO-FREQUENCY (RF) TO DIRECT CURRENT (DC) CONVERTER AND BIPOLAR QUANTIZED SUPERCURRENT GENERATOR (QSG)

    公开(公告)号:US20220065954A1

    公开(公告)日:2022-03-03

    申请号:US17005182

    申请日:2020-08-27

    Inventor: Matthew Beck

    Abstract: A radio-frequency (RF) to direct current (DC) converter is provided. When a DC electrical current is applied via a DC input port of the converter, the DC electrical current is shunted to ground through a Josephson junction (JJ) of the converter and substantially no DC electrical current flows through a resistor of the converter, and when an RF electrical current is applied via an RF input port of the converter, output trains of SFQ current pulses from a DC to SFQ converter of the RF-to-DC converter with pulse-to-pulse spacing inversely proportional to the RF electrical current frequency cause the JJ to switch at a rate commensurate with an RF frequency of the RF electrical current to generate a steady state voltage across the JJ linearly dependent on the RF frequency.

    SUPERCONDUCTING MULTI-WAY SWITCHES

    公开(公告)号:US20250105841A1

    公开(公告)日:2025-03-27

    申请号:US18475368

    申请日:2023-09-27

    Abstract: A device comprises a switch circuit and control lines. The switch circuit comprises a plurality of signal input/output ports, and a plurality of switch nodes, each switch node comprising a superconducting loop which comprises a plurality of Josephson junctions arranged in a ring configuration. The control lines are configured to selectively apply flux bias control signals to the switch nodes. The plurality of switch nodes is arranged to selectively configure a signal routing path between any pairwise combination of signal input/output ports of the plurality of signal input/output ports, in response to flux bias control signals selectively applied to the switch nodes.

    Balanced Inductor H-Tree for Powering Energy-Efficient SFQ Circuits

    公开(公告)号:US20230187801A1

    公开(公告)日:2023-06-15

    申请号:US17644453

    申请日:2021-12-15

    CPC classification number: H01P3/00

    Abstract: An embodiment of the invention may include a circuit structure. The circuit structure may include a wiring tree located between a feeding Josephson transmission line (FJTL) and a global bias line. The circuit may include the wiring tree having an H-tree structure, wherein each branch of the H-tree is connected by a current limiting junction of the FJTL, and wherein a single output port of the H-tree structure is connected to the global bias line. Another embodiment of the invention may include a circuit structure a circuit structure a plurality of feeding Josephson transmission lines (FJTLs) located between a feed line and a global bias line. The path of from the feed line through each FJTL and to the global bias line is substantially similar.

    RAPID SINGLE FLUX QUANTUM PULSE MULTIPLIER

    公开(公告)号:US20220190830A1

    公开(公告)日:2022-06-16

    申请号:US17118526

    申请日:2020-12-10

    Abstract: A method of generating an output signal based on a single flux quantum (SFQ) pulse includes receiving the SFQ pulse and splitting it into a first path and a second path. The split SFQ pulse of the second path is stored in a latch. A second splitting of the split SFQ pulse of the first path is provided to provide a first output signal and a second output signal of the first path. The second output signal is delayed by a delay Josephson transmission line (JTL). An output of the delay JTL is provided as a clock input to the latch. The first output of the first path is recombined with an output of the latch to provide an output signal.

    Metastability-free clockless single flux quantum logic circuitry

    公开(公告)号:US12231123B2

    公开(公告)日:2025-02-18

    申请号:US17971700

    申请日:2022-10-24

    Abstract: A device includes a logic circuit comprising a clockless single flux quantum logic gate which comprises a plurality of input ports, an output port, an output Josephson junction, and a plurality of dynamic storage loop circuits and isolation buffer circuits. The output Josephson junction is coupled to an output of each dynamic storage loop circuit and configured to drive the output port. Each isolation buffer circuit is coupled to a respective input port, and a respective dynamic storage loop circuit and configured to absorb a circulating current of an antifluxon which is injected into the respective dynamic storage loop circuit to prevent the antifluxon from being output from the respective input port, and to inject a fluxon into the respective dynamic storage loop circuit in response to a single flux quantum pulse applied to the respective input port, and annihilate an antifluxon present in the respective dynamic storage loop circuit.

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