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公开(公告)号：US20160064043A1
公开(公告)日：2016-03-03
申请号：US14476779
申请日：2014-09-04
Applicant: International Business Machines Corporation
Inventor： Michael DeCesaris , Luke D. Remis , Brian C. Totten
IPC: G11C5/14
Abstract: A method includes regulating voltage to a memory system responsive to a voltage signal received at a voltage feedback line, wherein the memory system includes a plurality of voltage sense line pairs in different locations within the memory system. The method further includes sequentially passing a voltage signal from each of the voltage sense line pairs to the voltage feedback line, and, for each voltage sense line pair, calculating a memory margin of the memory system based on memory operation while regulating voltage to the memory system responsive to the voltage signal from the voltage sense line pair. Still further, the method includes identifying the voltage sense line pair that provides the greatest memory margin, and then regulating voltage to the memory system responsive to the identified voltage sense line pair.
Abstract translation: 一种方法包括响应于在电压反馈线路处接收的电压信号来调节对存储器系统的电压，其中存储器系统在存储器系统内的不同位置包括多个电压检测线对。 该方法还包括将来自每个电压检测线对的电压信号顺序地传递到电压反馈线，并且对于每个电压检测线对，基于存储器操作计算存储器系统的存储器容限，同时调节对存储器的电压 系统响应于来自电压感测线对的电压信号。 此外，该方法包括识别提供最大存储器余量的电压检测线对，然后响应于所识别的电压感测线对来调节对存储器系统的电压。
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公开(公告)号：US08990465B2
公开(公告)日：2015-03-24
申请号：US13709015
申请日：2012-12-09
Applicant: International Business Machines Corporation
Inventor： Michael DeCesaris , John A. Henise, IV , Luke D. Remis , Gregory D. Sellman
IPC: G06F13/36 , G06F13/362 , G06F13/42 , G06F13/364
CPC classification number: G06F13/4291 , G06F13/3625 , G06F13/364 , G06F2213/0016 , G06F2213/0052
Abstract: The presence of devices attached to a bus are detected by a controller of a bus transmitting a signal on a channel of the bus, to cause each device to hold the channel to a first logical state for a duration of time that is unique to each device. The device that holds the channel to the first logical state for the longest duration of time is detected. Detected devices remain idle while undetected devices repeat holding the channel to the first logical state for the duration of time, until detected. All devices are detected when the channel returns to a second logical state.
Abstract translation: 连接到总线的设备的存在由总线的控制器检测，该总线在总线的通道上发送信号，以使每个设备将信道保持在第一逻辑状态，持续时间是每个设备唯一的 。 检测到将信道保持在第一逻辑状态持续最长持续时间的设备。 检测到的设备保持空闲，而未检测到的设备在持续时间内重复将信道保持到第一逻辑状态，直到被检测到。 当通道返回到第二逻辑状态时，检测所有设备。
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公开(公告)号：US20150046615A1
公开(公告)日：2015-02-12
申请号：US13961931
申请日：2013-08-08
Applicant: International Business Machines Corporation
Inventor： Michael DeCesaris , James J. Parsonese , Luke D. Remis , Gregory D. Sellman
CPC classification number: G06F13/1689 , G06F13/10 , G06F13/102 , G06F13/24 , G06F13/32 , G06F13/4022 , G11C14/0045
Abstract: Methods and systems for memory module communication control are disclosed. A method includes receiving a message associated with a memory module in communication with a controller via a bus including a clock line. Further, the method includes determining whether the bus is idle. The method also includes communicating a signal via the clock line regarding the message associated with the memory module in response to determining that the bus is idle.
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公开(公告)号：US08928393B1
公开(公告)日：2015-01-06
申请号：US14067273
申请日：2013-10-30
Applicant: International Business Machines Corporation
Inventor： Milton Cobo , Michael DeCesaris , Eric E. Pettersen , Luke D. Remis
Abstract: An apparatus comprising a temperature switch and a logic device, and a method of implementing multiple dynamic temperature thresholds. The temperature switch has a temperature sensor, a temperature threshold select input, and an output to a temperature threshold interrupt line, wherein the temperature switch selects a current temperature threshold from multiple predetermined temperature thresholds as determined by a state of the temperature threshold select input. The temperature switch causes an interrupt assertion on the temperature threshold interrupt line in response to the temperature sensor indicating a sensed temperature that exceeds the temperature threshold. The logic device has an input coupled to the temperature threshold interrupt line and a temperature threshold select output coupled to the temperature threshold select input of the temperature switch. The logic device automatically increments the temperature threshold select output in response to detecting an interrupt assertion on the temperature threshold interrupt line.
Abstract translation: 一种包括温度开关和逻辑装置的装置以及实现多个动态温度阈值的方法。 温度开关具有温度传感器，温度阈值选择输入和温度阈值中断线的输出，其中温度开关从由温度阈值选择输入的状态确定的多个预定温度阈值中选择当前温度阈值。 温度开关响应于温度传感器指示超过温度阈值的感测温度，导致温度阈值中断线上的中断断言。 逻辑器件具有耦合到温度阈值中断线的输入和耦合到温度开关的温度阈值选择输入的温度阈值选择输出。 响应于检测到温度阈值中断线上的中断断言，逻辑器件自动递增温度阈值选择输出。
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公开(公告)号：US20140170881A1
公开(公告)日：2014-06-19
申请号：US13719499
申请日：2012-12-19
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Michael DeCesaris , Luke D. Remis , Steven L. Vanderlinden , John K. Whetzel
IPC: H01R13/627
CPC classification number: H05K13/0491 , H01R13/6273 , H01R43/22 , Y10T29/53283
Abstract: Aspects of the present invention disclose a DIMM extraction tool for extracting a DIMM from a DIMM socket. Exemplary embodiments of the DIMM extraction tool include a frame adapted for use as an air baffle within the DIMM socket, a first arm and a second arm pivotably connected to the frame. When the first arm and second arm are in a resting position, the first and second arm respectively engage a first resting detent and a second resting detent to prevent pivotable rotation of the first arm and second arm in exemplary embodiments of the DIMM extraction tool. When the first arm and second arm are in a working position, the first arm and second arm respectively are adapted to releasably engage the DIMM and bias resilient latching arm of the DIMM socket.
Abstract translation: 本发明的方面公开了一种用于从DIMM插槽提取DIMM的DIMM提取工具。 DIMM提取工具的示例性实施例包括适于在DIMM插槽内用作空气挡板的框架，第一臂和可枢转地连接到框架的第二臂。 当第一臂和第二臂处于静止位置时，第一臂和第二臂分别接合第一静止制动器和第二静止制动器，以防止在DIMM提取工具的示例性实施例中第一臂和第二臂的可枢转的旋转。 当第一臂和第二臂处于工作位置时，第一臂和第二臂分别适于可释放地接合DIMM并且偏置DIMM插座的弹性锁定臂。
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Patent Agency Ranking
6.发明申请公开(公告)号：US20160011621A1
公开(公告)日：2016-01-14
申请号：US14330687
申请日：2014-07-14
Applicant: International Business Machines Corporation
Inventor： Michael DeCesaris , Luke D. Remis , Brian C. Totten
IPC: G05F3/08
Abstract: A computer program product includes a computer readable storage medium having program instructions embodied therewith, wherein the program instructions are executable by a processor to cause the processor to perform a method. The method comprises obtaining an activity level for each of a plurality of functions of an integrated circuit, wherein each function has a different physical location on the integrated circuit. The method further includes dynamically adjusting an amount of current supplied to the integrated circuit by each of a plurality of power stages of a DC voltage regulator to meet the current requirements of the plurality of functions and to control power losses between the power stages and the functions, wherein each power stage has a different physical location along a perimeter of the integrated circuit.
Abstract translation: 一种计算机程序产品包括具有实施的程序指令的计算机可读存储介质，其中程序指令可由处理器执行以使处理器执行方法。 该方法包括为集成电路的多个功能中的每一个获得活动级别，其中每个功能在集成电路上具有不同的物理位置。 该方法还包括通过DC电压调节器的多个功率级中的每一个来动态地调节提供给集成电路的电流量，以满足多个功能的电流要求并控制功率级与功能之间的功率损耗 ，其中每个功率级沿着所述集成电路的周边具有不同的物理位置。
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公开(公告)号：US08954619B1
公开(公告)日：2015-02-10
申请号：US13960883
申请日：2013-08-07
Applicant: International Business Machines Corporation
Inventor： Michael DeCesaris , James J. Parsonese , Luke D. Remis , Gregory D. Sellman
CPC classification number: G06F13/1689 , G06F13/10 , G06F13/102 , G06F13/24 , G06F13/32 , G06F13/4022 , G11C14/0045
Abstract: Methods and systems for memory module communication control are disclosed. A method includes receiving a message associated with a memory module in communication with a controller via a bus including a clock line. Further, the method includes determining whether the bus is idle. The method also includes communicating a signal via the clock line regarding the message associated with the memory module in response to determining that the bus is idle.
Abstract translation: 公开了用于存储器模块通信控制的方法和系统。 一种方法包括经由包括时钟线的总线接收与与控制器通信的存储器模块相关联的消息。 此外，该方法包括确定总线是否空闲。 响应于确定总线空闲，该方法还包括经由时钟线传送关于与存储器模块相关联的消息的信号。
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公开(公告)号：US20140115222A1
公开(公告)日：2014-04-24
申请号：US13657501
申请日：2012-10-22
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Michael DeCesaris , Luke D. Remis , Gregory D. Sellman , Steven L. Vanderlinden
IPC: G06F13/20
CPC classification number: G06F13/4291 , G06F13/4054
Abstract: A serial peripheral interface (SPI) system including a bus adapter is disclosed. The bus adapter may include a data converter that may be adapted to receive respective first and second data from a first master output peripheral input (MOPI) line and a chip select line from a SPI master device. The data converter may also be adapted to interleave the first and second data, and the data converter may be adapted to transmit the interleaved first and second data synchronously with a second clock signal on a second MOPI line. The bus adapter may also include a clock rate adjuster adapted to generate the second clock signal to transmit to a SPI peripheral device. The second clock signal may be adapted to enable the SPI peripheral device to read the transmitted data.
Abstract translation: 公开了一种包括总线适配器的串行外设接口（SPI）系统。 总线适配器可以包括数据转换器，其可以适于从第一主输出外围输入（MOPI）线和来自SPI主器件的芯片选择线接收相应的第一和第二数据。 数据转换器还可以适于交织第一和第二数据，并且数据转换器可以适于在第二MOPI线上与第二时钟信号同步地发送交错的第一和第二数据。 总线适配器还可以包括适于产生第二时钟信号以传输到SPI外围设备的时钟速率调节器。 第二时钟信号可以适于使得SPI外围设备能够读取所发送的数据。
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公开(公告)号：US20150316973A1
公开(公告)日：2015-11-05
申请号：US14265405
申请日：2014-04-30
Applicant: International Business Machines Corporation
Inventor： Gary D. Cudak , Michael DeCesaris , Luke D. Remis , Brian C. Totten
IPC: G06F1/32
Abstract: According to one exemplary embodiment, a method for load optimization using cable-associated voltage drop is provided. The method may include receiving a plurality of tasks for processing by a plurality of electronic devices. The method may also include determining a power loss value for one or more power cables powering each of the plurality of electronic devices. The method may further include assigning the plurality of tasks to one or more of the plurality of electronic devices based on the power loss value for the one or more power cables powering each of the plurality of electronic devices.
Abstract translation: 根据一个示例性实施例，提供了一种使用电缆相关联的电压降进行负载优化的方法。 该方法可以包括接收由多个电子设备进行处理的多个任务。 该方法还可以包括确定为多个电子设备中的每一个供电的一个或多个电力电缆的功率损耗值。 该方法还可以包括基于为多个电子设备中的每一个供电的一个或多个电力电缆的功率损耗值，将多个任务分配给多个电子设备中的一个或多个。
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公开(公告)号：US09026685B2
公开(公告)日：2015-05-05
申请号：US13961931
申请日：2013-08-08
Applicant: International Business Machines Corporation
Inventor： Michael DeCesaris , James J. Parsonese , Luke D. Remis , Gregory D. Sellman
CPC classification number: G06F13/1689 , G06F13/10 , G06F13/102 , G06F13/24 , G06F13/32 , G06F13/4022 , G11C14/0045
Abstract: Methods and systems for memory module communication control are disclosed. A method includes receiving a message associated with a memory module in communication with a controller via a bus including a clock line. Further, the method includes determining whether the bus is idle. The method also includes communicating a signal via the clock line regarding the message associated with the memory module in response to determining that the bus is idle.
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