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公开(公告)号:US09915701B2
公开(公告)日:2018-03-13
申请号:US15425159
申请日:2017-02-06
Applicant: International Business Machines Corporation
Inventor: Michael Fee , Ronald J. Frishmuth , Mary P. Kusko , Cedric Lichtenau
IPC: G01R31/317 , G01R31/3177
CPC classification number: G01R31/31723 , G01R31/31703 , G01R31/3172 , G01R31/31725 , G01R31/3177 , G01R31/318541 , G01R31/318566
Abstract: Aspects include techniques for bypassing an encoded latch on a chip during a test-pattern scan and using on-chip circuitry to generate a desired encoded pattern, which is inserted into a scan-bypassed latch, to test the on-chip circuitry for defects. A computer-implemented method may include applying a global control bit to the chip; initializing a scan of the chip while bypassing the encoded latch; and applying an extra scan clock to initiate the encoded latch after completing the scan, wherein the encoded latch is updated with check bits generated by the on-chip circuitry.
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公开(公告)号:US09858190B2
公开(公告)日:2018-01-02
申请号:US14606432
申请日:2015-01-27
Applicant: International Business Machines Corporation
Inventor: Ekaterina M. Ambroladze , Timothy C. Bronson , Garrett M. Drapala , Michael Fee , Matthias Klein , Pak-kin Mak , Robert J. Sonnelitter, III , Gary E. Strait
IPC: G06F12/08 , G06F12/0855 , G06F12/0831
CPC classification number: G06F12/0855 , G06F12/0833 , G06F2212/1021 , G06F2212/608 , G06F2212/621
Abstract: Maintaining store order with high throughput in a distributed shared memory system. A request is received for a first ordered data store and a coherency check is initiated. A signal is sent that pipelining of a second ordered data store can be initiated. If a delay condition is encountered during the coherency check for the first ordered data store, rejection of the first ordered data store is signaled. If a delay condition is not encountered during the coherency check for the first ordered data store, a signal is sent indicating a readiness to continue pipelining of the second ordered data store.
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公开(公告)号:US20170261555A1
公开(公告)日:2017-09-14
申请号:US15425159
申请日:2017-02-06
Applicant: International Business Machines Corporation
Inventor: Michael Fee , Ronald J. Frishmuth , Mary P. Kusko , Cedric Lichtenau
IPC: G01R31/317 , G01R31/3177
CPC classification number: G01R31/31723 , G01R31/31703 , G01R31/3172 , G01R31/31725 , G01R31/3177 , G01R31/318541 , G01R31/318566
Abstract: Aspects include techniques for bypassing an encoded latch on a chip during a test-pattern scan and using on-chip circuitry to generate a desired encoded pattern, which is inserted into a scan-bypassed latch, to test the on-chip circuitry for defects. A computer-implemented method may include applying a global control bit to the chip; initializing a scan of the chip while bypassing the encoded latch; and applying an extra scan clock to initiate the encoded latch after completing the scan, wherein the encoded latch is updated with check bits generated by the on-chip circuitry.
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公开(公告)号:US20160232099A1
公开(公告)日:2016-08-11
申请号:US14616784
申请日:2015-02-09
Applicant: International Business Machines Corporation
Inventor: Ekaterina M. Ambroladze , Deanna P. Berger , Garrett M. Drapala , Michael Fee , Pak-kin Mak , Arthur J. O'Neill, JR. , Diana L. Orf
CPC classification number: G06F12/0868 , G06F3/0619 , G06F3/065 , G06F3/0685 , G06F11/10 , G06F11/1446 , G06F12/0802 , G06F12/0804 , G06F12/0808 , G06F12/0888 , G06F12/0891 , G06F12/0897 , G06F2212/1016 , G06F2212/311 , G06F2212/60 , G06F2212/608
Abstract: In an approach for backing up designated data located in a cache, data stored within an index of a cache is identified, wherein the data has an associated designation indicating that the data is applicable to be backed up to a higher level memory. It is determined that the data stored to the cache has been updated. A status associated with the data is adjusted, such that the adjusted status indicates that the data stored to the cache has not been changed. A copy of the data is created. The copy of the data is stored to the higher level memory.
Abstract translation: 在用于备份位于高速缓存中的指定数据的方法中,识别存储在高速缓存的索引内的数据,其中数据具有指示该数据可应用于备份到较高级存储器的相关联的指定。 确定存储到高速缓存的数据已被更新。 调整与数据相关联的状态,使得调整状态指示存储到高速缓存的数据未被改变。 创建数据的副本。 数据的副本存储到较高级别的内存。
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公开(公告)号:US20160139954A1
公开(公告)日:2016-05-19
申请号:US14542746
申请日:2014-11-17
Applicant: International Business Machines Corporation
Inventor: Michael Fee , Ute Gaertner , Lisa C. Heller , Thomas Koehler , Frank Lehnert , Jennifer A. Navarro
IPC: G06F9/48
CPC classification number: G06F9/45554 , G06F9/45533 , G06F9/4812 , G06F9/5016 , G06F9/5088 , G06F2209/5018 , G06F2209/5021
Abstract: Methods and apparatuses for performing a quiesce operation in a multithread environment is provided. A processor receives a first thread quiesce request from a first thread executing on the processor. A processor sends a first processor quiesce request to a system controller to initiate a quiesce operation. A processor performs one or more operations of the first thread based, at least in part, on receiving a response from the system controller.
Abstract translation: 提供了在多线程环境中执行静止操作的方法和装置。 处理器从处理器上执行的第一线程接收第一线程静默请求。 处理器向系统控制器发送第一处理器静默请求以启动静默操作。 至少部分地,处理器基于从系统控制器接收响应,执行第一线程的一个或多个操作。
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公开(公告)号:US09298468B2
公开(公告)日:2016-03-29
申请号:US14095393
申请日:2013-12-03
Applicant: International Business Machines Corporation
Inventor: Ekaterina M. Ambroladze , Deanna Postles Dunn Berger , Michael Fee , Christine C. Jones , Arthur J. O'Neill , Diana Lynn Orf , Robert J. Sonnelitter
CPC classification number: G06F9/3867 , G06F11/3419 , G06F11/3466 , G06F2201/88
Abstract: A pipelined processing device includes: a pipeline controller configured to receive at least one instruction associated with an operation from each of a plurality of subcontrollers, and input the at least one instruction into a pipeline; and a pipeline counter configured to receive an active time value from each of the plurality of subcontrollers, the active time value indicating at least a portion of a time taken to process the at least one instruction, the pipeline controller configured to route the active time value to a shared pipeline storage for performance analysis.
Abstract translation: 流水线处理装置包括:流水线控制器,被配置为从多个子控制器中的每一个接收与操作相关联的至少一个指令,并将所述至少一个指令输入到流水线中; 以及流水线计数器,被配置为从所述多个子控制器中的每一个接收活动时间值,所述活动时间值指示处理所述至少一个指令所花费的时间的至少一部分,所述流水线控制器被配置为将所述活动时间值 到共享流水线存储进行性能分析。
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公开(公告)号:US11880304B2
公开(公告)日:2024-01-23
申请号:US17664722
申请日:2022-05-24
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor: Taylor J Pritchard , Aaron Tsai , Richard Joseph Branciforte , Ashraf ElSharif , Gregory William Alexander , Deanna Postles Dunn Berger , Michael Fee
IPC: G06F12/0811
CPC classification number: G06F12/0811 , G06F2212/1021
Abstract: To facilitate an efficient processing of contended cache lines, a cache controller that is associated with a requestor receives a fetch request for data from the requestor. The fetch request is associated with a cache scope designation. If the data is in a high-level cache (e.g., L1 cache) associated with the requestor, the cache controller returns the requested data to the requestor. If the data is not in the high-level cache or if the data is not within the cache pool identified by the cache scope of search designation, and/or if obtaining the data is contentious, the controller returns a cache miss, undeliverable data, and request done instruction to the requestor. Such scheme allows or permits address contention events when the requestor deems such events are necessary and/or when important. As such, address contention events, performance, latencies, increased executions times, inefficient use of resources, may be diminished.
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公开(公告)号:US20230385195A1
公开(公告)日:2023-11-30
申请号:US17664722
申请日:2022-05-24
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor: Taylor J. Pritchard , Aaron Tsai , Richard Joseph Branciforte , Ashraf ElSharif , Gregory William Alexander , Deanna Postles Dunn Berger , Michael Fee
IPC: G06F12/0811
CPC classification number: G06F12/0811 , G06F2212/1021
Abstract: To facilitate an efficient processing of contended cache lines, a cache controller that is associated with a requestor receives a fetch request for data from the requestor. The fetch request is associated with a cache scope designation. If the data is in a high-level cache (e.g., L1 cache) associated with the requestor, the cache controller returns the requested data to the requestor. If the data is not in the high-level cache or if the data is not within the cache pool identified by the cache scope of search designation, and/or if obtaining the data is contentious, the controller returns a cache miss, undeliverable data, and request done instruction to the requestor. Such scheme allows or permits address contention events when the requestor deems such events are necessary and/or when important. As such, address contention events, performance, latencies, increased executions times, inefficient use of resources, may be diminished.
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公开(公告)号:US10176002B2
公开(公告)日:2019-01-08
申请号:US14573025
申请日:2014-12-17
Applicant: International Business Machines Corporation
Inventor: Michael Fee , Ute Gaertner , Lisa C. Heller , Thomas Koehler , Frank Lehnert , Jennifer A. Navarro
Abstract: Methods and apparatuses for performing a quiesce operation in a multithread environment is provided. A processor receives a first thread quiesce request from a first thread executing on the processor. A processor sends a first processor quiesce request to a system controller to initiate a quiesce operation. A processor performs one or more operations of the first thread based, at least in part, on receiving a response from the system controller.
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公开(公告)号:US20180107617A1
公开(公告)日:2018-04-19
申请号:US15842920
申请日:2017-12-15
Applicant: International Business Machines Corporation
Inventor: Ekaterina M. Ambroladze , Deanna P. Berger , Michael Fee , Arthur J. O'Neill, JR.
CPC classification number: G06F13/1673 , G06F13/1652 , G06F13/4022 , G06F13/4234
Abstract: In an approach for managing data transfer across a bus shared by processors, a request for a first set of data is received from a first processor. A request for a second set of data is received from a second processor. First portions of the first set of data and the second set of data are written to a buffer. Additional portions of each set of data are written to the buffer as portions are received. It is determined that a portion of the first set of data has a higher priority to the bus than a portion of the second set of data based on a priority scheme, wherein the priority scheme is based on return progress of each respective set of data having at least a portion of data in the buffer. The portion of the first set of data is granted access to the bus.
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