Method and apparatus for joint adaptation of two-/multi-dimensional equalizer and partial response target

    公开(公告)号:US10026441B2

    公开(公告)日:2018-07-17

    申请号:US15648985

    申请日:2017-07-13

    Abstract: The present disclosure relates to a method and apparatus for processing of multi-dimensional readback signal from magnetic recording or optical, physical data recording so as to reduce/control Inter Symbol Interference (ISI) and noise within acceptable limits. The method is based on Partial Response Maximum Likelihood (PRML) detection and takes care of time varying channel conditions. In an embodiment, the filter coefficients of both the equalizer and the partial response (PR) target are jointly adapted to account for the channel condition for both separable and non-separable targets thus reducing signal detection complexity. In an aspect, the disclosure provides an apparatus that incorporates an adaptation engine along with the equalizer and the PR target that updates filter coefficients of both the equalizer and the PR target following the formulated mathematical equations.

    Reed-Solomon decoders and decoding methods

    公开(公告)号:US10439643B2

    公开(公告)日:2019-10-08

    申请号:US15660940

    申请日:2017-07-26

    Abstract: Embodiments of the present disclosure provide a high speed low latency rate configurable soft decision and hard decision based pipelined Reed-Solomon (RS) decoder architecture suitable for optical communication and storage. The proposed RS decoder is a configurable RS decoder that is configured to monitor the channel and adjust code parameters based on channel capacity. The proposed RS decoder includes interpolation and factorization free Low-Complexity-Chase (LCC) decoding to implement soft-decision decoder (SDD). The proposed RS decoder generates test vectors and feeds these to a pipelined 2-stage hard decision decoder (HDD). The proposed RS decoder architecture computes error locator polynomial in exactly 2t clock cycles without parallelism and supports high throughput, and further computes error evaluator polynomial in exactly t cycles. The present disclosure provides a 2-stage pipelined decoder to operate at least latency possible and reduced size of delay buffer.

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