公开(公告)号：US20180108675A1

公开(公告)日：2018-04-19

申请号：US15785627

申请日：2017-10-17

Applicant: Infineon Technologies AG

Inventor： Sebastian Schmidt ,  Donald Dibra ,  Oliver Hellmund ,  Peter Irsigler ,  Andreas Meiser ,  Hans-Joachim Schulze ,  Martina Seider-Schmidt ,  Robert Wiesner

IPC: H01L27/12 ,  H01L21/762 ,  H01L21/02 ,  H01L21/265 ,  H01L29/06 ,  H01L21/84

Abstract: In accordance with an embodiment of an integrated circuit, a cavity is buried in a semiconductor body below a first surface of the semiconductor body. An active area portion of the semiconductor body is arranged between the first surface and the cavity. The integrated circuit further includes a trench isolation structure configured to provide a lateral electric isolation of the active area portion.

公开(公告)号：US10553675B2

公开(公告)日：2020-02-04

申请号：US15785627

申请日：2017-10-17

Applicant: Infineon Technologies AG

Inventor： Sebastian Schmidt ,  Donald Dibra ,  Oliver Hellmund ,  Peter Irsigler ,  Andreas Meiser ,  Hans-Joachim Schulze ,  Martina Seider-Schmidt ,  Robert Wiesner

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/265 ,  H01L21/762 ,  H01L21/84 ,  H01L27/12

Abstract: In accordance with an embodiment of an integrated circuit, a cavity is buried in a semiconductor body below a first surface of the semiconductor body. An active area portion of the semiconductor body is arranged between the first surface and the cavity. The integrated circuit further includes a trench isolation structure configured to provide a lateral electric isolation of the active area portion.

公开(公告)号：US20140251408A1

公开(公告)日：2014-09-11

申请号：US14282886

申请日：2014-05-20

Applicant: Infineon Technologies AG

Inventor： Donald Dibra ,  Christoph Kadow ,  Markus Zundel

IPC: H01L35/32

CPC classification number: H01L35/32 ,  G01K1/08 ,  G01K7/02

Abstract: An embodiment of the invention relates to a Seebeck temperature difference sensor that may be formed in a trench on a semiconductor device. A portion of the sensor may be substantially surrounded by an electrically conductive shield. A plurality of junctions may be included to provide a higher Seebeck sensor voltage. The shield may be electrically coupled to a local potential, or left electrically floating. A portion of the shield may be formed as a doped well in the semiconductor substrate on which the semiconductor device is formed, or as a metal layer substantially covering the sensor. The shield may be formed as a first oxide layer on a sensor trench wall with a conductive shield formed on the first oxide layer, and a second oxide layer formed on the conductive shield. An absolute temperature sensor may be coupled in series with the Seebeck temperature difference sensor.

Abstract translation: 本发明的实施例涉及可以形成在半导体器件上的沟槽中的塞贝克温差传感器。 传感器的一部分可以被导电屏蔽件基本上包围。 可以包括多个结以提供更高的塞贝克传感器电压。 屏蔽可以电耦合到局部电位，或者电耦合到电浮置。 屏蔽的一部分可以形成为半导体器件形成的半导体衬底中的掺杂阱，或者形成为基本覆盖传感器的金属层。 屏蔽件可以形成为在传感器沟槽壁上的第一氧化物层，其中形成在第一氧化物层上的导电屏蔽层和形成在导电屏蔽上的第二氧化物层。 绝对温度传感器可以与塞贝克温差传感器串联耦合。

公开(公告)号：US09899367B2

公开(公告)日：2018-02-20

申请号：US15153276

申请日：2016-05-12

Applicant: Infineon Technologies AG

Inventor： Kai Esmark ,  Yiqun Cao ,  Donald Dibra

IPC: H01L29/66 ,  H01L27/02 ,  H01L27/088 ,  H01L29/10 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L27/0255 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/1095 ,  H01L29/7816

Abstract: An embodiment of an integrated circuit includes a minimum lateral dimension of a semiconductor well at a first surface of a semiconductor body. The integrated circuit further includes a first lateral DMOSFET having a load path electrically coupled to a load pin. The first lateral DMOSFET is configured to control a load current through a load element electrically coupled to the load pin. A minimum lateral dimension of a drain region of the first lateral DMOSFET at the first surface of the semiconductor body is more than 50% greater than the minimum lateral dimension.

公开(公告)号：US09865792B2

公开(公告)日：2018-01-09

申请号：US14282886

申请日：2014-05-20

Applicant: Infineon Technologies AG

Inventor： Donald Dibra ,  Christoph Kadow ,  Markus Zundel

IPC: G01K7/04 ,  H01L35/32 ,  G01K1/08 ,  G01K7/02

CPC classification number: H01L35/32 ,  G01K1/08 ,  G01K7/02

Abstract: An embodiment of the invention relates to a Seebeck temperature difference sensor that may be formed in a trench on a semiconductor device. A portion of the sensor may be substantially surrounded by an electrically conductive shield. A plurality of junctions may be included to provide a higher Seebeck sensor voltage. The shield may be electrically coupled to a local potential, or left electrically floating. A portion of the shield may be formed as a doped well in the semiconductor substrate on which the semiconductor device is formed, or as a metal layer substantially covering the sensor. The shield may be formed as a first oxide layer on a sensor trench wall with a conductive shield formed on the first oxide layer, and a second oxide layer formed on the conductive shield. An absolute temperature sensor may be coupled in series with the Seebeck temperature difference sensor.

公开(公告)号：US20160336308A1

公开(公告)日：2016-11-17

申请号：US15153276

申请日：2016-05-12

Applicant: Infineon Technologies AG

Inventor： Kai Esmark ,  Yiqun Cao ,  Donald Dibra

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L23/50 ,  H01L29/866 ,  H01L29/08 ,  H01L27/088

CPC classification number: H01L27/0255 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/1095 ,  H01L29/7816

Abstract: An embodiment of an integrated circuit includes a minimum lateral dimension of a semiconductor well at a first surface of a semiconductor body. The integrated circuit further includes a first lateral DMOSFET having a load path electrically coupled to a load pin. The first lateral DMOSFET is configured to control a load current through a load element electrically coupled to the load pin. A minimum lateral dimension of a drain region of the first lateral DMOSFET at the first surface of the semiconductor body is more than 50% greater than the minimum lateral dimension.

Abstract translation: 集成电路的实施例包括在半导体本体的第一表面处的半导体阱的最小横向尺寸。 集成电路还包括具有电耦合到负载引脚的负载路径的第一横向DMOSFET。 第一横向DMOSFET被配置为控制通过电耦合到负载引脚的负载元件的负载电流。 在半导体主体的第一表面处的第一横向DMOSFET的漏极区域的最小横向尺寸比最小横向尺寸大50％以上。