公开(公告)号：US11127693B2

公开(公告)日：2021-09-21

申请号：US16710044

申请日：2019-12-11

Applicant: Infineon Technologies AG

Inventor： Johann Gatterbauer ,  Katrin Albers ,  Joerg Busch ,  Klaus Goller ,  Norbert Mais ,  Marianne Kolitsch ,  Michael Nelhiebel ,  Rainer Pelzer ,  Bernhard Weidgans

IPC: H01L23/00 ,  B81B7/00 ,  H01L23/58

Abstract: A semiconductor device includes a structured interlayer on a substrate, a structured power metallization on the structured interlayer, and a barrier on the structured power metallization. The barrier is configured to prevent diffusion of at least one of water, water ions, sodium ions, potassium ions, chloride ions, fluoride ions, and sulphur ions towards the structured power metallization. A first defined edge of the structured interlayer faces the same direction as a first defined edge of the structured power metallization and extends beyond the first defined edge of the structured power metallization by at least 0.5 microns. The structured interlayer has a compressive residual stress at room temperature and the structured power metallization generates a tensile stress at room temperature that is at least partly counteracted by the compressive residual stress of the structured interlayer. The first defined edge of the structured power metallization has a sidewall which slopes inward.

公开(公告)号：US20210082861A1

公开(公告)日：2021-03-18

申请号：US17090941

申请日：2020-11-06

Applicant: Infineon Technologies AG

Inventor： Joachim Mahler ,  Michael Bauer ,  Jochen Dangelmaier ,  Reimund Engl ,  Johann Gatterbauer ,  Frank Hille ,  Michael Huettinger ,  Werner Kanert ,  Heinrich Koerner ,  Brigitte Ruehle ,  Francisco Javier Santos Rodriguez ,  Antonio Vellei

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/29 ,  H01L21/02 ,  H01L23/495

Abstract: In various embodiments, a method of forming an electrical contact is provided. The method may include depositing, by atomic layer deposition, a passivation layer over at least a region of a metal surface, wherein the passivation layer may include aluminum oxide, and electrically contacting the region of the metal surface with a metal contact structure, wherein the metal contact structure may include copper.

公开(公告)号：US20170141090A1

公开(公告)日：2017-05-18

申请号：US14945170

申请日：2015-11-18

Applicant: Infineon Technologies AG

Inventor： Dietrich Bonart ,  Bernhard Weidgans ,  Johann Gatterbauer ,  Thomas Gross ,  Martina Heigl

IPC: H01L25/16 ,  H01L33/60 ,  H01L21/66 ,  H01L23/532 ,  H01L23/00 ,  H01L23/528 ,  H01L23/522 ,  H01L33/62 ,  H01L21/768

CPC classification number: H01L25/167 ,  H01L21/76834 ,  H01L21/76877 ,  H01L22/20 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/552 ,  H01L24/03 ,  H01L24/06 ,  H01L27/14692 ,  H01L31/055 ,  H01L33/20 ,  H01L33/405 ,  H01L33/46 ,  H01L33/60 ,  H01L33/62 ,  H01L2224/05144 ,  H01L2224/48227 ,  H01L2924/12041 ,  H01L2933/0058 ,  H01L2933/0066

Abstract: A semiconductor device includes an active region disposed in a semiconductor substrate and an uppermost metal level including metal lines, where the uppermost metal level is disposed over the semiconductor substrate. Contact pads are disposed at a major surface of the semiconductor device, where the contact pads are coupled to the metal lines in the uppermost metal level. An isolation region separates the contact pads disposed at the major surface. Adjacent contact pads are electrically isolated from one another by a portion of the isolation region. Reflective structures are disposed between the upper metal level and the contact pads, where each of the reflective structures that is directly over the active region completely overlaps an associated portion of the isolation region separating the contact pad.

公开(公告)号：US11735534B2

公开(公告)日：2023-08-22

申请号：US17333186

申请日：2021-05-28

Applicant: Infineon Technologies AG

Inventor： Harry Walter Sax ,  Johann Gatterbauer ,  Wolfgang Lehnert ,  Evelyn Napetschnig ,  Michael Rogalli

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L23/564 ,  H01L21/56 ,  H01L23/3142 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/0382 ,  H01L2224/05687 ,  H01L2924/365

Abstract: A chip package is provided. The chip package may include at least one chip, an exposed metal region and a metal protection layer structure over the exposed metal region and configured to protect the metal region from oxidation. The protection layer structure includes a low-temperature deposited oxide, and a hydrothermally converted metal oxide layer over the protection layer structure.

公开(公告)号：US20200227278A1

公开(公告)日：2020-07-16

申请号：US16743571

申请日：2020-01-15

Applicant: Infineon Technologies AG

Inventor： Johann Gatterbauer ,  Wolfgang Lehnert ,  Norbert Mais ,  Verena Muhr ,  Edmund Riedl ,  Harry Sax

IPC: H01L21/48 ,  H01L21/02 ,  H01L21/56 ,  H01L23/495 ,  H01L23/31

Abstract: A method of forming a layer structure is provided. The method may include plasma-treating a metal surface with a hydrogen-containing plasma, thereby forming nucleophilic groups over the metal surface, and forming an organic layer over the metal surface, wherein the organic layer comprises silane and is covalently bonded to the nucleophilic groups.

公开(公告)号：US10607972B2

公开(公告)日：2020-03-31

申请号：US15974299

申请日：2018-05-08

Applicant: Infineon Technologies AG

Inventor： Dietrich Bonart ,  Bernhard Weidgans ,  Johann Gatterbauer ,  Thomas Gross ,  Martina Heigl

IPC: H01L25/16 ,  H01L27/146 ,  H01L33/20 ,  H01L23/552 ,  H01L33/44 ,  H01L33/38 ,  H01L51/52 ,  H01L21/768 ,  H01L21/66 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L23/00 ,  H01L31/055 ,  H01L33/40 ,  H01L33/46 ,  H01L33/60 ,  H01L33/62

Abstract: A semiconductor device includes an active region disposed in a semiconductor substrate and an uppermost metal level including metal lines, where the uppermost metal level is disposed over the semiconductor substrate. Contact pads are disposed at a major surface of the semiconductor device, where the contact pads are coupled to the metal lines in the uppermost metal level. An isolation region separates the contact pads disposed at the major surface. Adjacent contact pads are electrically isolated from one another by a portion of the isolation region. Reflective structures are disposed between the upper metal level and the contact pads, where each of the reflective structures that is directly over the active region completely overlaps an associated portion of the isolation region separating the contact pad.

公开(公告)号：US10461056B2

公开(公告)日：2019-10-29

申请号：US15600857

申请日：2017-05-22

Applicant: Infineon Technologies AG

Inventor： Joachim Mahler ,  Michael Bauer ,  Jochen Dangelmaier ,  Reimund Engl ,  Johann Gatterbauer ,  Frank Hille ,  Michael Huettinger ,  Werner Kanert ,  Heinrich Koerner ,  Brigitte Ruehle ,  Francisco Javier Santos Rodriguez ,  Antonio Vellei

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/29 ,  H01L21/02 ,  H01L23/495

Abstract: In various embodiments, a chip package is provided. The chip package may include a chip, a metal contact structure including a non-noble metal and electrically contacting the chip, a packaging material, and a protective layer including or essentially consisting of a portion formed at an interface between a portion of the metal contact structure and the packaging material, wherein the protective layer may include a noble metal, wherein the portion of the protective layer may include a plurality of regions free from the noble metal, and wherein the regions free from the noble metal may provide an interface between the packaging material and the non-noble metal of the metal contact structure.

公开(公告)号：US20170271313A1

公开(公告)日：2017-09-21

申请号：US15615031

申请日：2017-06-06

Applicant: Infineon Technologies AG

Inventor： Dietrich Bonart ,  Bernhard Weidgans ,  Johann Gatterbauer ,  Thomas Gross ,  Martina Heigl

IPC: H01L25/16 ,  H01L33/40 ,  H01L33/46 ,  H01L33/62 ,  H01L23/532 ,  H01L21/66 ,  H01L21/768 ,  H01L23/00 ,  H01L23/528 ,  H01L23/522 ,  H01L31/055 ,  H01L33/60

CPC classification number: H01L25/167 ,  H01L21/76834 ,  H01L21/76877 ,  H01L22/20 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/552 ,  H01L24/03 ,  H01L24/06 ,  H01L27/14692 ,  H01L31/055 ,  H01L33/20 ,  H01L33/405 ,  H01L33/46 ,  H01L33/60 ,  H01L33/62 ,  H01L2224/05144 ,  H01L2224/48227 ,  H01L2924/12041 ,  H01L2933/0058 ,  H01L2933/0066

Abstract: A semiconductor device includes an active region disposed in a semiconductor substrate and an uppermost metal level including metal lines, where the uppermost metal level is disposed over the semiconductor substrate. Contact pads are disposed at a major surface of the semiconductor device, where the contact pads are coupled to the metal lines in the uppermost metal level. An isolation region separates the contact pads disposed at the major surface. Adjacent contact pads are electrically isolated from one another by a portion of the isolation region. Reflective structures are disposed between the upper metal level and the contact pads, where each of the reflective structures that is directly over the active region completely overlaps an associated portion of the isolation region separating the contact pad.

公开(公告)号：US20170110423A1

公开(公告)日：2017-04-20

申请号：US15292219

申请日：2016-10-13

Applicant: Infineon Technologies AG

Inventor： Johann Gatterbauer ,  Bernhard Weidgans ,  Dietrich Bonart ,  Thomas Gross ,  Martina Debie

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L21/0272 ,  H01L21/0331 ,  H01L24/03 ,  H01L2224/05082 ,  H01L2224/05084 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171

Abstract: According to various embodiments, a method may include: forming a first layer on a surface using a first lift-off process; forming a second layer over the first layer using a second lift-off process; wherein the second lift-off process is configured such that the second layer covers at least one sidewall of the first layer at least partially.

公开(公告)号：US09502248B1

公开(公告)日：2016-11-22

申请号：US14884869

申请日：2015-10-16

Applicant: Infineon Technologies AG

Inventor： Johann Gatterbauer ,  Bernhard Weidgans ,  Dietrich Bonart ,  Thomas Gross ,  Martina Debie

IPC: H01L21/44 ,  H01L21/033

CPC classification number: H01L24/05 ,  H01L21/0272 ,  H01L21/0331 ,  H01L24/03 ,  H01L2224/05082 ,  H01L2224/05084 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171

Abstract: According to various embodiments, a method may include: forming a first layer on a surface using a first lift-off process; forming a second layer over the first layer using a second lift-off process; wherein the second lift-off process is configured such that the second layer covers at least one sidewall of the first layer at least partially.

Abstract translation: 根据各种实施例，一种方法可以包括：使用第一剥离过程在表面上形成第一层; 使用第二剥离工艺在所述第一层上形成第二层; 其中所述第二剥离过程被配置为使得所述第二层至少部分地覆盖所述第一层的至少一个侧壁。