公开(公告)号：US20230170393A1

公开(公告)日：2023-06-01

申请号：US17921781

申请日：2021-04-28

Applicant: Infineon Technologies AG

Inventor： Helmut Brech ,  John Twynam

IPC: H01L29/40 ,  H01L23/29 ,  H01L23/31 ,  H01L29/20 ,  H01L29/778

CPC classification number: H01L29/402 ,  H01L23/291 ,  H01L23/3171 ,  H01L29/2003 ,  H01L29/7786

Abstract: A Group III nitride-based transistor device is provided that has a gate drain capacitance (CGD), a drain source capacitance (CDS) and a drain source on resistance (RDSon). A ratio of the gate drain capacitance (CGD) at a drain source voltage (VDS) of 0V, CGD (0V), and the gate drain capacitance CGD at a value of VDS>0V, CGDV, is at least 3:1, wherein VDS is less than 15V.

公开(公告)号：US20230155000A1

公开(公告)日：2023-05-18

申请号：US18093434

申请日：2023-01-05

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Rudolf Berger ,  Helmut Brech ,  Olaf Storbeck ,  Haifeng Sun ,  John Twynam

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/265 ,  H01L21/268 ,  H01L23/29 ,  H01L23/31 ,  H01L29/10 ,  H01L29/20 ,  H01L29/205 ,  H01L29/417 ,  H01L29/778

CPC classification number: H01L29/66462 ,  H01L21/0217 ,  H01L21/268 ,  H01L21/26546 ,  H01L23/291 ,  H01L23/3171 ,  H01L29/205 ,  H01L29/1033 ,  H01L29/2003 ,  H01L29/7786 ,  H01L29/41725

Abstract: A method includes providing a semiconductor body, forming a thermosensitive element on or within the semiconductor body, forming a structured laser-reflective mask on the upper surface of the semiconductor body that covers the thermosensitive element and includes first and second openings, and performing a laser thermal annealing process that transmits laser energy through the first and second openings and into the semiconductor body, wherein the thermosensitive element comprises a critical temperature at which the thermosensitive element is irreparably damaged, wherein the laser thermal annealing process brings portions of the semiconductor body that are underneath the first and second openings to above the critical temperature, and wherein during the laser thermal annealing process the thermosensitive element remains below the critical temperature.

公开(公告)号：US20210336015A1

公开(公告)日：2021-10-28

申请号：US17228973

申请日：2021-04-13

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Helmut Brech ,  John Twynam

IPC: H01L29/40 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L21/765 ,  H01L29/66

Abstract: In an embodiment, a Group III nitride-based transistor device includes a source electrode, a drain electrode and a gate electrode positioned on a first major surface of a Group III nitride based-based layer, wherein the gate electrode is laterally arranged between the source electrode and the drain electrode, a passivation layer arranged on the first major surface and a field plate coupled to the source electrode, the field plate having a lower surface arranged on the passivation layer. The field plate is laterally arranged between and laterally spaced apart from the gate electrode and the drain electrode.

公开(公告)号：US11929405B2

公开(公告)日：2024-03-12

申请号：US17228973

申请日：2021-04-13

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Helmut Brech ,  John Twynam

IPC: H01L29/40 ,  H01L21/765 ,  H01L23/29 ,  H01L23/31 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/402 ,  H01L21/765 ,  H01L23/291 ,  H01L23/3171 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/401 ,  H01L29/66462 ,  H01L29/7786

Abstract: In an embodiment, a Group III nitride-based transistor device includes a source electrode, a drain electrode and a gate electrode positioned on a first major surface of a Group III nitride based-based layer, wherein the gate electrode is laterally arranged between the source electrode and the drain electrode, a passivation layer arranged on the first major surface and a field plate coupled to the source electrode, the field plate having a lower surface arranged on the passivation layer. The field plate is laterally arranged between and laterally spaced apart from the gate electrode and the drain electrode.

公开(公告)号：US11869963B2

公开(公告)日：2024-01-09

申请号：US17733009

申请日：2022-04-29

Applicant: Infineon Technologies AG

Inventor： John Twynam ,  Albert Birner ,  Helmut Brech

IPC: H01L29/778 ,  H01L21/02 ,  H01L21/265 ,  H01L29/04 ,  H01L29/06 ,  H01L29/10 ,  H01L29/20 ,  H01L29/205 ,  H01L29/207 ,  H01L29/32 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L21/0254 ,  H01L21/26546 ,  H01L29/04 ,  H01L29/0684 ,  H01L29/1029 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/207 ,  H01L29/32 ,  H01L29/66462

Abstract: A semiconductor device includes a support substrate having a first surface capable of supporting the epitaxial growth of at least one III-V semiconductor and a second surface opposing the first surface, at least one mesa positioned on the first surface, each mesa including an epitaxial III-V semiconductor-based multi-layer structure on the first surface of the support substrate, the III-V semiconductor-based multi-layer structure forming a boundary with the first surface and a parasitic channel suppression region positioned laterally adjacent the boundary.

公开(公告)号：US20210336043A1

公开(公告)日：2021-10-28

申请号：US17237178

申请日：2021-04-22

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Helmut Brech ,  John Twynam

IPC: H01L29/778 ,  H01L29/40 ,  H01L29/66

Abstract: In an embodiment, a Group III nitride-based transistor device includes a first passivation layer arranged on a first major surface of a Group III nitride-based layer, a second passivation layer arranged on the first passivation layer, a source ohmic contact, a drain ohmic contact and a gate positioned on the first major surface of a Group III nitride-based layer, and a field plate, the field plate being laterally arranged between and spaced apart from the gate and the drain ohmic contact.

公开(公告)号：US11581418B2

公开(公告)日：2023-02-14

申请号：US16894223

申请日：2020-06-05

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Rudolf Berger ,  Helmut Brech ,  Olaf Storbeck ,  Haifeng Sun ,  John Twynam

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/265 ,  H01L21/268 ,  H01L23/29 ,  H01L23/31 ,  H01L29/10 ,  H01L29/20 ,  H01L29/205 ,  H01L29/417 ,  H01L29/778

Abstract: A semiconductor body having a base carrier portion and a type III-nitride semiconductor portion is provided. The type III-nitride semiconductor portion includes a heterojunction and two-dimensional charge carrier gas. One or more ohmic contacts are formed in the type III-nitride semiconductor portion, the ohmic contacts forming an ohmic connection with the two-dimensional charge carrier gas. A gate structure is configured to control a conductive state of the two-dimensional charge carrier gas. Forming the one or more ohmic contacts comprises forming a structured laser-reflective mask on the upper surface of the type III-nitride semiconductor portion, implanting dopant atoms into the upper surface of the type III-nitride semiconductor portion, and performing a laser thermal anneal that activates the implanted dopant atoms.

公开(公告)号：US11342451B2

公开(公告)日：2022-05-24

申请号：US16697490

申请日：2019-11-27

Applicant: Infineon Technologies AG

Inventor： John Twynam ,  Albert Birner ,  Helmut Brech

IPC: H01L29/778 ,  H01L21/02 ,  H01L21/265 ,  H01L29/04 ,  H01L29/06 ,  H01L29/10 ,  H01L29/20 ,  H01L29/205 ,  H01L29/207 ,  H01L29/32 ,  H01L29/66

Abstract: A semiconductor device includes a support substrate having a first surface capable of supporting the epitaxial growth of at least one III-V semiconductor and a second surface opposing the first surface, at least one mesa positioned on the first surface, each mesa including an epitaxial III-V semiconductor-based multi-layer structure on the first surface of the support substrate, the III-V semiconductor-based multi-layer structure forming a boundary with the first surface and a parasitic channel suppression region positioned laterally adjacent the boundary.

公开(公告)号：US12087830B2

公开(公告)日：2024-09-10

申请号：US17237178

申请日：2021-04-22

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Helmut Brech ,  John Twynam

IPC: H01L29/40 ,  H01L21/765 ,  H01L23/29 ,  H01L23/31 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/402 ,  H01L21/765 ,  H01L23/291 ,  H01L23/3171 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/401 ,  H01L29/66462 ,  H01L29/7786

Abstract: In an embodiment, a Group III nitride-based transistor device includes a first passivation layer arranged on a first major surface of a Group III nitride-based layer, a second passivation layer arranged on the first passivation layer, a source ohmic contact, a drain ohmic contact and a gate positioned on the first major surface of a Group III nitride-based layer, and a field plate, the field plate being laterally arranged between and spaced apart from the gate and the drain ohmic contact.

公开(公告)号：US20250159917A1

公开(公告)日：2025-05-15

申请号：US19025359

申请日：2025-01-16

Applicant: Infineon Technologies AG

Inventor： Helmut Brech ,  Albert Birner ,  John Twynam

IPC: H10D30/01 ,  H01L21/02 ,  H01L21/78 ,  H10D30/47 ,  H10D62/824 ,  H10D62/85 ,  H10D64/23

Abstract: A semiconductor device includes a plurality of mesas, each mesa including an epitaxial Group III nitride-based multi-layer structure, an insulating matrix having an upper surface and a lower surface, wherein side faces of the mesas are embedded in the insulating matrix and a top surface of the mesas is substantially coplanar with the upper surface of the insulating matrix, and a metallization structure including a gate finger and a drain finger arranged on the top surface of each mesa, a drain bus that electrically couples a first drain finger arranged on a first mesa with a second drain finger arranged on a second mesa, and a gate bus that electrically couples a first gate finger arranged on the first mesa with a second gate finger arranged on a second mesa.