公开(公告)号：US10355087B2

公开(公告)日：2019-07-16

申请号：US15062370

申请日：2016-03-07

Applicant: Infineon Technologies AG

Inventor： Martin Vielemeyer ,  Andreas Meiser ,  Till Schloesser ,  Franz Hirler ,  Martin Poelzl

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L21/265

Abstract: A semiconductor device includes a transistor in a semiconductor substrate having a main surface. The transistor includes a source region, a drain region, a channel region, a drift zone, a gate electrode, and a gate dielectric adjacent to the gate electrode. The gate electrode is disposed adjacent to at least two sides of the channel region. The channel region and the drift zone are disposed along a first direction parallel to the main surface between the source region and the drain region. The gate dielectric has a thickness that varies at different positions of the gate electrode.

公开(公告)号：US20150137224A1

公开(公告)日：2015-05-21

申请号：US14082491

申请日：2013-11-18

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Rolf Weis ,  Franz Hirler ,  Martin Vielemeyer ,  Markus Zundel ,  Peter Irsigler

IPC: H01L29/78 ,  H01L27/12 ,  H01L29/66 ,  H01L29/10 ,  H01L29/40 ,  H01L29/417

CPC classification number: H01L29/4175 ,  H01L27/1203 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/66696 ,  H01L29/7824 ,  H01L29/7825 ,  H01L29/7826 ,  H01L29/7835

Abstract: A semiconductor device comprises a transistor formed in a semiconductor body having a first main surface. The transistor comprises a source region, a drain region, a channel region, a drift zone, a source contact electrically connected to the source region, a drain contact electrically connected to the drain region, and a gate electrode at the channel region. The channel region and the drift zone are disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface. The channel region has a shape of a first ridge extending along the first direction. One of the source contact and the drain contact is adjacent to the first main surface, the other one of the source contact and the drain contact is adjacent to a second main surface that is opposite to the first main surface.

Abstract translation: 半导体器件包括形成在具有第一主表面的半导体本体中的晶体管。 晶体管包括源极区，漏极区，沟道区，漂移区，电连接到源极区的源极接触，电连接到漏极区的漏极接触，以及沟道区处的栅电极。 沟道区域和漂移区域沿着源极区域和漏极区域之间的第一方向设置，第一方向平行于第一主表面。 通道区域具有沿着第一方向延伸的第一脊的形状。 源极接触和漏极接触中的一个与第一主表面相邻，源极接触和漏极接触中的另一个与与第一主表面相对的第二主表面相邻。

公开(公告)号：US09917160B2

公开(公告)日：2018-03-13

申请号：US15098789

申请日：2016-04-14

Applicant: Infineon Technologies AG

Inventor： Andrew Christopher Graeme Wood ,  Oliver Blank ,  Martin Poelzl ,  Martin Vielemeyer

IPC: H01L29/40 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L27/06 ,  H01L29/04 ,  H01L27/11526 ,  H01L29/423 ,  H01L29/8605 ,  H01L29/861 ,  H01L29/16 ,  H01L29/20

CPC classification number: H01L29/407 ,  H01L27/0629 ,  H01L27/11526 ,  H01L29/04 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7804 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/8605 ,  H01L29/861

Abstract: A semiconductor device includes a semiconductor body, having a first surface, a gate electrode structure, which includes polycrystalline silicon, of an IGFET in a first trench extending from the first surface into the semiconductor body. The device also includes a semiconductor element, which is different from the gate electrode structure of the IGFET and includes polycrystalline silicon, in a second trench extending from the first surface into the semiconductor body, wherein the polycrystalline silicon of the IGFET and of the semiconductor element different therefrom ends below a top side of an insulation layer adjoining the first surface of the semiconductor body.

公开(公告)号：US20160190256A1

公开(公告)日：2016-06-30

申请号：US15062370

申请日：2016-03-07

Applicant: Infineon Technologies AG

Inventor： Martin Vielemeyer ,  Andreas Meiser ,  Till Schloesser ,  Franz Hirler ,  Martin Poelzl

IPC: H01L29/10 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/1083 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/2822 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66681 ,  H01L29/66696 ,  H01L29/66704 ,  H01L29/7816 ,  H01L29/7825

Abstract: A semiconductor device includes a transistor in a semiconductor substrate having a main surface. The transistor includes a source region, a drain region, a channel region, a drift zone, a gate electrode, and a gate dielectric adjacent to the gate electrode. The gate electrode is disposed adjacent to at least two sides of the channel region. The channel region and the drift zone are disposed along a first direction parallel to the main surface between the source region and the drain region. The gate dielectric has a thickness that varies at different positions of the gate electrode.

Abstract translation: 半导体器件包括具有主表面的半导体衬底中的晶体管。 晶体管包括源极区，漏极区，沟道区，漂移区，栅电极和与栅电极相邻的栅极电介质。 栅电极设置成与沟道区域的至少两侧相邻。 沟道区域和漂移区域沿着平行于源极区域和漏极区域之间的主表面的第一方向设置。 栅极电介质具有在栅电极的不同位置处变化的厚度。

公开(公告)号：US10439030B2

公开(公告)日：2019-10-08

申请号：US15646152

申请日：2017-07-11

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Rolf Weis ,  Franz Hirler ,  Martin Vielemeyer ,  Markus Zundel ,  Peter Irsigler

IPC: H01L29/92 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/40 ,  H01L29/10 ,  H01L27/12 ,  H01L29/06

Abstract: A semiconductor device includes a transistor in a semiconductor body having a first main surface. The transistor includes: a source contact electrically connected to a source region; a drain contact electrically connected to a drain region; a gate electrode at the channel region, the channel region and a drift zone disposed along a first direction between the source and drain regions, the first direction being parallel to the first main surface, the channel region patterned into a ridge by adjacent gate trenches formed in the first main surface, the adjacent gate trenches spaced apart in a second direction perpendicular to the first direction, a longitudinal axis of the ridge extending in the first direction and a longitudinal axis of the gate trenches extending in the first direction; and at least one of the source and drain contacts being adjacent to a second main surface opposite the first main surface.

公开(公告)号：US20170317176A1

公开(公告)日：2017-11-02

申请号：US15646152

申请日：2017-07-11

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Rolf Weis ,  Franz Hirler ,  Martin Vielemeyer ,  Markus Zundel ,  Peter Irsigler

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L27/12

CPC classification number: H01L29/4175 ,  H01L27/1203 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/66696 ,  H01L29/7824 ,  H01L29/7825 ,  H01L29/7826 ,  H01L29/7835

Abstract: A semiconductor device includes a transistor in a semiconductor body having a first main surface. The transistor includes: a source contact electrically connected to a source region; a drain contact electrically connected to a drain region; a gate electrode at the channel region, the channel region and a drift zone disposed along a first direction between the source and drain regions, the first direction being parallel to the first main surface, the channel region patterned into a ridge by adjacent gate trenches formed in the first main surface, the adjacent gate trenches spaced apart in a second direction perpendicular to the first direction, a longitudinal axis of the ridge extending in the first direction and a longitudinal axis of the gate trenches extending in the first direction; and at least one of the source and drain contacts being adjacent to a second main surface opposite the first main surface.

公开(公告)号：US09356141B2

公开(公告)日：2016-05-31

申请号：US14447896

申请日：2014-07-31

Applicant: Infineon Technologies AG

Inventor： Andrew Christopher Graeme Wood ,  Oliver Blank ,  Martin Poelzl ,  Martin Vielemeyer

IPC: H01L27/11 ,  H01L29/04 ,  H01L29/78 ,  H01L29/66 ,  H01L27/115 ,  H01L29/423 ,  H01L29/8605 ,  H01L29/861 ,  H01L29/16 ,  H01L29/20

CPC classification number: H01L29/407 ,  H01L27/0629 ,  H01L27/11526 ,  H01L29/04 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7804 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/8605 ,  H01L29/861

Abstract: The disclosure relates to a semiconductor device including a semiconductor body, having a first surface, a gate electrode structure, which includes polycrystalline silicon, of an IGFET in a first trench extending from the first surface into the semiconductor body. The device also includes a semiconductor element, which is different from the gate electrode structure of the IGFET and includes polycrystalline silicon, in a second trench extending from the first surface into the semiconductor body, wherein the polycrystalline silicon of the IGFET and of the semiconductor element different therefrom ends below a top side of an insulation layer adjoining the first surface of the semiconductor body.

Abstract translation: 本公开涉及一种半导体器件，其包括在从第一表面延伸到半导体本体的第一沟槽中具有IGFET的第一表面，第一表面，包括多晶硅的栅电极结构的半导体本体。 所述器件还包括半导体元件，所述半导体元件与所述IGFET的栅电极结构不同，并且在从所述第一表面延伸到所述半导体本体的第二沟槽中包括多晶硅，其中所述IGFET的多晶硅和所述半导体元件 不同之处在与半导体本体的第一表面相邻的绝缘层的顶侧下方。

公开(公告)号：US20150091088A1

公开(公告)日：2015-04-02

申请号：US14043971

申请日：2013-10-02

Applicant: Infineon Technologies AG

Inventor： Martin Vielemeyer ,  Andreas Meiser ,  Till Schloesser ,  Franz Hirler ,  Martin Poelzl

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/1083 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/2822 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66681 ,  H01L29/66696 ,  H01L29/66704 ,  H01L29/7816 ,  H01L29/7825

Abstract: An integrated circuit includes a transistor in a semiconductor substrate having a main surface. The transistor includes a source region, a drain region, a channel region, a drift zone, a gate electrode, and a gate dielectric adjacent to the gate electrode. The gate electrode is disposed adjacent to at least two sides of the channel region. The channel region and the drift zone are disposed along a first direction parallel to the main surface between the source region and the drain region. The gate dielectric has a thickness that varies at different positions of the gate electrode.

Abstract translation: 集成电路包括具有主表面的半导体衬底中的晶体管。 晶体管包括源极区，漏极区，沟道区，漂移区，栅电极和与栅电极相邻的栅极电介质。 栅电极设置成与沟道区域的至少两侧相邻。 沟道区域和漂移区域沿着平行于源极区域和漏极区域之间的主表面的第一方向设置。 栅极电介质具有在栅电极的不同位置处变化的厚度。

公开(公告)号：US09735243B2

公开(公告)日：2017-08-15

申请号：US14082491

申请日：2013-11-18

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Rolf Weis ,  Franz Hirler ,  Martin Vielemeyer ,  Markus Zundel ,  Peter Irsigler

IPC: H01L27/115 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/40 ,  H01L29/10 ,  H01L27/12 ,  H01L29/06

CPC classification number: H01L29/4175 ,  H01L27/1203 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/66696 ,  H01L29/7824 ,  H01L29/7825 ,  H01L29/7826 ,  H01L29/7835

Abstract: A semiconductor device comprises a transistor formed in a semiconductor body having a first main surface. The transistor comprises a source region, a drain region, a channel region, a drift zone, a source contact electrically connected to the source region, a drain contact electrically connected to the drain region, and a gate electrode at the channel region. The channel region and the drift zone are disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface. The channel region has a shape of a first ridge extending along the first direction. One of the source contact and the drain contact is adjacent to the first main surface, the other one of the source contact and the drain contact is adjacent to a second main surface that is opposite to the first main surface.

公开(公告)号：US20150041816A1

公开(公告)日：2015-02-12

申请号：US14447896

申请日：2014-07-31

Applicant: Infineon Technologies AG

Inventor： Andrew Christopher Graeme Wood ,  Oliver Blank ,  Martin Poelzl ,  Martin Vielemeyer

IPC: H01L29/78 ,  H01L29/04 ,  H01L29/66

CPC classification number: H01L29/407 ,  H01L27/0629 ,  H01L27/11526 ,  H01L29/04 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7804 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/8605 ,  H01L29/861

Abstract: The disclosure relates to a semiconductor device including a semiconductor body, having a first surface, a gate electrode structure, which includes polycrystalline silicon, of an IGFET in a first trench extending from the first surface into the semiconductor body. The device also includes a semiconductor element, which is different from the gate electrode structure of the IGFET and includes polycrystalline silicon, in a second trench extending from the first surface into the semiconductor body, wherein the polycrystalline silicon of the IGFET and of the semiconductor element different therefrom ends below a top side of an insulation layer adjoining the first surface of the semiconductor body.

Abstract translation: 本公开涉及一种半导体器件，其包括在从第一表面延伸到半导体本体的第一沟槽中具有IGFET的第一表面，第一表面，包括多晶硅的栅电极结构的半导体本体。 所述器件还包括半导体元件，所述半导体元件与所述IGFET的栅电极结构不同，并且在从所述第一表面延伸到所述半导体本体的第二沟槽中包括多晶硅，其中所述IGFET的多晶硅和所述半导体元件 不同之处在与半导体本体的第一表面相邻的绝缘层的顶侧下方。