公开(公告)号：US10050591B2

公开(公告)日：2018-08-14

申请号：US15078298

申请日：2016-03-23

Applicant: Infineon Technologies AG

Inventor： Saurabh Goel ,  Richard Wilson ,  Haedong Jang

IPC: H03F3/19 ,  H03F3/21 ,  H03F1/56

Abstract: An amplifier is configured to amplify an RF signal as between an input terminal and an output terminal across a wideband frequency range. A first LC network is connected to the input terminal and has first and second reactive components. A first switching device is connected between the first and second reactive components and couples both the first and second reactive components to the input terminal in an ON state, and disconnects the second reactive component from the input terminal in an OFF state. A second LC network is connected to the output terminal and has third and fourth reactive components. A second switching device is connected between the third and fourth reactive components and couples both the third and fourth reactive components to the output terminal in an ON state and disconnects the fourth reactive component from the output terminal in an OFF state.

公开(公告)号：US20160294340A1

公开(公告)日：2016-10-06

申请号：US14673928

申请日：2015-03-31

Applicant: Infineon Technologies AG

Inventor： Saurabh Goel ,  Alexander Komposch ,  Cynthia Blair ,  Cristian Gozzi

IPC: H03F3/21 ,  H01L23/498 ,  H01L25/16 ,  H03F3/19 ,  H01L25/065 ,  H01L23/66 ,  H01L25/00 ,  H03F1/02 ,  H01L23/495 ,  H01L25/07

Abstract: A multi-cavity package includes a single metal flange having first and second opposing main surfaces, a circuit board attached to the first main surface of the single metal flange, the circuit board having a plurality of openings which expose different regions of the first main surface of the single metal flange, and a plurality of semiconductor dies each of which is disposed in one of the openings in the circuit board and attached to the first main surface of the single metal flange. The circuit board includes a plurality of metal traces for electrically interconnecting the semiconductor dies to form a circuit. A corresponding method of manufacturing is also provided.

Abstract translation: 多空腔包装包括具有第一和第二相对主表面的单个金属凸缘，附接到单个金属凸缘的第一主表面的电路板，电路板具有多个开口，其暴露第一主表面的不同区域 的单个金属凸缘，以及多个半导体管芯，每个半导体管芯设置在电路板的一个开口中并且附接到单个金属法兰的第一主表面。 电路板包括用于电连接半导体管芯以形成电路的多个金属迹线。 还提供了相应的制造方法。

公开(公告)号：US20150243649A1

公开(公告)日：2015-08-27

申请号：US14186840

申请日：2014-02-21

Applicant: Infineon Technologies AG

Inventor： Helmut Brech ,  Matthias Zigldrum ,  Albert Birner ,  Richard Wilson ,  Saurabh Goel

IPC: H01L27/06 ,  H01L23/00 ,  H01L23/528 ,  H01L23/522 ,  H01L49/02

CPC classification number: H01L27/0629 ,  H01L23/4824 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/528 ,  H01L24/05 ,  H01L24/09 ,  H01L28/40 ,  H01L29/7802 ,  H01L29/7816 ,  H01L2223/6655 ,  H01L2223/6672 ,  H01L2224/04042 ,  H01L2224/0603 ,  H01L2224/0616 ,  H01L2224/0912 ,  H01L2224/48195 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2924/1205 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13063 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/1421 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2924/0001

Abstract: A power transistor die includes a transistor formed in a semiconductor body. The transistor has a gate terminal, an output terminal and a third terminal. The gate terminal controls a conduction channel between the output terminal and the third terminal. The power transistor die further includes a structured first metal layer disposed on and insulated from the semiconductor body. The structured first metal layer is connected to the output terminal of the transistor. The power transistor die also includes a first bond pad disposed on and insulated from the semiconductor body. The first bond pad forms an output terminal of the power transistor die and is capacitively coupled to the structured first metal layer so as to form a series capacitance between the output terminal of the transistor and the first bond pad. A power semiconductor package including the power transistor die is also provided.

Abstract translation: 功率晶体管管芯包括形成在半导体本体中的晶体管。 晶体管具有栅极端子，输出端子和第三端子。 栅极端子控制输出端子和第三端子之间的导通通道。 功率晶体管管芯还包括设置在半导体本体上并与半导体本体绝缘的结构化的第一金属层。 结构化的第一金属层连接到晶体管的输出端。 功率晶体管管芯还包括设置在半导体本体上并与半导体本体绝缘的第一接合焊盘。 第一接合焊盘形成功率晶体管管芯的输出端子，并且与结构化的第一金属层电容耦合，以便在晶体管的输出端和第一接合焊盘之间形成串联电容。 还提供了包括功率晶体管管芯的功率半导体封装。

公开(公告)号：US20170279419A1

公开(公告)日：2017-09-28

申请号：US15078298

申请日：2016-03-23

Applicant: Infineon Technologies AG

Inventor： Saurabh Goel ,  Richard Wilson ,  Haedong Jang

IPC: H03F3/19 ,  H03F3/21 ,  H03F1/56

CPC classification number: H03F3/19 ,  H03F1/565 ,  H03F3/193 ,  H03F3/21 ,  H03F3/245 ,  H03F2200/111 ,  H03F2200/222 ,  H03F2200/252 ,  H03F2200/267 ,  H03F2200/421 ,  H03F2200/451 ,  H03F2200/48

Abstract: An amplifier is configured to amplify an RF signal as between an input terminal and an output terminal across a wideband frequency range. A first LC network is connected to the input terminal and has first and second reactive components. A first switching device is connected between the first and second reactive components and couples both the first and second reactive components to the input terminal in an ON state, and disconnects the second reactive component from the input terminal in an OFF state. A second LC network is connected to the output terminal and has third and fourth reactive components. A second switching device is connected between the third and fourth reactive components and couples both the third and fourth reactive components to the output terminal in an ON state and disconnects the fourth reactive component from the output terminal in in an OFF state.