公开(公告)号：US12107128B2

公开(公告)日：2024-10-01

申请号：US18461042

申请日：2023-09-05

Applicant: Infineon Technologies AG

Inventor： Saurabh Roy ,  Thomas Aichinger ,  Hans-Joachim Schulze

IPC: H01L29/66 ,  H01L29/16 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L29/1608 ,  H01L29/516 ,  H01L29/66053 ,  H01L29/78391

Abstract: A method of producing a semiconductor device includes forming a plurality of transistor cells in a SiC substrate and electrically connected in parallel to form a transistor having a specified operating temperature range. Forming each transistor cell includes forming a gate structure having a gate electrode, and a gate dielectric stack separating the gate electrode from the SiC substrate and including a ferroelectric insulator. The method further includes doping the ferroelectric insulator with a doping material such that the Curie temperature of the ferroelectric insulator is in a range above the specified operating temperature range of the transistor.

公开(公告)号：US20240371772A1

公开(公告)日：2024-11-07

申请号：US18640821

申请日：2024-04-19

Applicant: Infineon Technologies AG

Inventor： Saurabh Roy ,  Josef Schätz ,  Dethard Peters ,  Hans-Joachim Schulze

IPC: H01L23/532 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78

Abstract: A vertical power semiconductor device is proposed. The vertical power semiconductor device includes a silicon carbide (SIC) semiconductor body including a trench structure. The trench structure extends into the SiC semiconductor body at a first surface of the SiC semiconductor body. The trench structure includes a gate electrode and a gate dielectric arranged between the gate electrode and the SiC semiconductor body. An interlayer dielectric structure is arranged on the trench structure. The interlayer dielectric structure includes at least one of an aluminum nitride layer, a silicon nitride layer, an aluminum oxide layer, or a boron nitride layer. The vertical power semiconductor device further includes a source or emitter electrode on the interlayer dielectric structure.

公开(公告)号：US20240090355A1

公开(公告)日：2024-03-14

申请号：US18454852

申请日：2023-08-24

Applicant: Infineon Technologies AG

Inventor： Saurabh Roy ,  Josef Anton Moser ,  Hans-Joachim Schulze

IPC: H10N99/00

CPC classification number: H10N99/03

Abstract: A piezoresistive transistor device includes a first transistor cell having a first piezoelectric material body and a first piezoresistive material body arranged in a stacked configuration. A first electrical resistance of the first piezoresistive material body is dependent upon a voltage applied across the first piezoelectric material body by way of a pressure applied by the first piezoelectric material body to the first piezoresistive material body. A second transistor cell includes a second piezoelectric material body and a second piezoresistive material body arranged in a stacked configuration. A second electrical resistance of the second piezoresistive material body is dependent upon a voltage applied across the second piezoelectric material body by way of a pressure applied by the second piezoelectric material body to the second piezoresistive material body. An internal electrical interconnect is configured to electrically connect the first electrical resistance and the second electrical resistance in series or in parallel.

公开(公告)号：US20230178615A1

公开(公告)日：2023-06-08

申请号：US18072965

申请日：2022-12-01

Applicant: Infineon Technologies AG

Inventor： Saurabh Roy ,  Hans-Joachim Schulze ,  Oliver Blank ,  Josef Anton Moser ,  Thomas Aichinger

IPC: H01L29/423 ,  H01L29/10 ,  H01L29/40 ,  H01L29/78

CPC classification number: H01L29/4236 ,  H01L29/1095 ,  H01L29/1033 ,  H01L29/407 ,  H01L29/7813

Abstract: A power transistor device includes a semiconductor substrate, a gate trench extending into the semiconductor substrate, a transistor gate provided in the gate trench, and an insulating structure formed between the transistor gate and a side wall of the gate trench. The insulating structure is configured to electrically insulate the transistor gate from a channel region which extends along the side wall of the gate trench. The insulating structure includes a layer of piezoelectric material.

公开(公告)号：US20230035144A1

公开(公告)日：2023-02-02

申请号：US17387504

申请日：2021-07-28

Applicant: Infineon Technologies AG

Inventor： Saurabh Roy ,  Thomas Aichinger ,  Hans-Joachim Schulze

IPC: H01L29/16 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes a SiC substrate and a plurality of transistor cells formed in the SiC substrate and electrically connected in parallel to form a transistor. Each transistor cell includes a gate structure including a gate electrode and a gate dielectric stack separating the gate electrode from the SiC substrate. The gate dielectric stack includes a ferroelectric insulator. The transistor has a specified operating temperature range, and the ferroelectric insulator is doped with a doping material such that the Curie temperature of the ferroelectric insulator is in a range above the specified operating temperature range of the transistor. A corresponding method of producing the semiconductor device is also described.

公开(公告)号：US20240055257A1

公开(公告)日：2024-02-15

申请号：US18360459

申请日：2023-07-27

Applicant: Infineon Technologies AG

Inventor： Saurabh Roy ,  Werner Schustereder ,  Ravi Keshav Joshi ,  Hans-Joachim Schulze ,  Daria Krasnozhon

IPC: H01L21/04 ,  H01L29/45 ,  H01L29/16 ,  H01L29/04

CPC classification number: H01L21/0485 ,  H01L29/452 ,  H01L29/1608 ,  H01L29/045

Abstract: The disclosure relates to a method for manufacturing a contact on a SiC substrate, wherein the method includes: providing a crystalline SiC substrate; modifying a crystal structure in a surface area of the SiC substrate such that a carbon-enriched SiC portion is generated in the surface area; forming a contact layer on the SiC substrate by depositing a metallic contact material onto the surface area that includes the carbon-enriched SiC portion; and thermal annealing of at least a part of the carbon-enriched SiC portion of the SiC substrate and at least a part of the contact layer, such that a ternary metallic phase portion including at least the metallic contact material, silicon, and carbon is generated. Furthermore, SiC semiconductor devices are described, which include a crystalline SiC substrate and a contact layer including a ternary metallic phase portion directly in contact with the SiC substrate surface.

公开(公告)号：US11791383B2

公开(公告)日：2023-10-17

申请号：US17387504

申请日：2021-07-28

Applicant: Infineon Technologies AG

Inventor： Saurabh Roy ,  Thomas Aichinger ,  Hans-Joachim Schulze

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/16 ,  H01L29/51

CPC classification number: H01L29/1608 ,  H01L29/516 ,  H01L29/66053 ,  H01L29/78391

Abstract: A semiconductor device includes a SiC substrate and a plurality of transistor cells formed in the SiC substrate and electrically connected in parallel to form a transistor. Each transistor cell includes a gate structure including a gate electrode and a gate dielectric stack separating the gate electrode from the SiC substrate. The gate dielectric stack includes a ferroelectric insulator. The transistor has a specified operating temperature range, and the ferroelectric insulator is doped with a doping material such that the Curie temperature of the ferroelectric insulator is in a range above the specified operating temperature range of the transistor. A corresponding method of producing the semiconductor device is also described.