公开(公告)号：US20170148705A1

公开(公告)日：2017-05-25

申请号：US15425614

申请日：2017-02-06

Applicant: Infineon Techonologies Americas Corp.

Inventor： Eung San Cho

IPC: H01L23/367 ,  H01L23/00 ,  H01F1/03 ,  H01L23/498 ,  H01F27/24 ,  H01L25/18 ,  H01L23/31

CPC classification number: H01L23/3675 ,  H01F1/0306 ,  H01F27/24 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/645 ,  H01L24/31 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/072 ,  H01L25/18 ,  H01L2224/2919 ,  H01L2224/32013 ,  H01L2224/32245 ,  H01L2224/32265 ,  H01L2224/37124 ,  H01L2224/37144 ,  H01L2224/37147 ,  H01L2224/40245 ,  H01L2224/41173 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48108 ,  H01L2224/48227 ,  H01L2224/48245 ,  H01L2224/49173 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83424 ,  H01L2224/83447 ,  H01L2224/84424 ,  H01L2224/84447 ,  H01L2224/84801 ,  H01L2224/8484 ,  H01L2224/8485 ,  H01L2224/85424 ,  H01L2224/85447 ,  H01L2924/0665 ,  H01L2924/10253 ,  H01L2924/1033 ,  H01L2924/13055 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/14252 ,  H01L2924/1426 ,  H01L2924/1427 ,  H01L2924/15724 ,  H01L2924/15747 ,  H01L2924/19011 ,  H01L2924/19042 ,  H01L2924/19102 ,  H05K1/0209 ,  H05K1/165 ,  H05K1/181 ,  H05K1/184 ,  H05K1/185 ,  H05K2201/1003 ,  H05K2201/10166 ,  H01L2924/00014

Abstract: A semiconductor package includes a semiconductor die comprising a control transistor and a sync transistor, an integrated output inductor comprising a winding around a core, and coupled to the semiconductor die. The winding comprises a plurality of conductive clips situated above a printed circuit board (PCB) and connected to a plurality of conductive segments in the PCB. The control transistor and the sync transistor are configured as a half-bridge. The integrated output inductor is coupled to a switched node of the half-bridge. At least one of the plurality of conductive clips includes a partially etched portion and a non-etched portion. The semiconductor die is attached to the integrated output inductor by a die attach material. The semiconductor die and the integrated output inductor are encapsulated in a molding compound.

公开(公告)号：US09911679B2

公开(公告)日：2018-03-06

申请号：US15425614

申请日：2017-02-06

Applicant: Infineon Techonologies Americas Corp.

Inventor： Eung San Cho

IPC: H01L23/367 ,  H05K1/18 ,  H01L25/18 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01F27/24 ,  H01F1/03

CPC classification number: H01L23/3675 ,  H01F1/0306 ,  H01F27/24 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/645 ,  H01L24/31 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/072 ,  H01L25/18 ,  H01L2224/2919 ,  H01L2224/32013 ,  H01L2224/32245 ,  H01L2224/32265 ,  H01L2224/37124 ,  H01L2224/37144 ,  H01L2224/37147 ,  H01L2224/40245 ,  H01L2224/41173 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48108 ,  H01L2224/48227 ,  H01L2224/48245 ,  H01L2224/49173 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83424 ,  H01L2224/83447 ,  H01L2224/84424 ,  H01L2224/84447 ,  H01L2224/84801 ,  H01L2224/8484 ,  H01L2224/8485 ,  H01L2224/85424 ,  H01L2224/85447 ,  H01L2924/0665 ,  H01L2924/10253 ,  H01L2924/1033 ,  H01L2924/13055 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/14252 ,  H01L2924/1426 ,  H01L2924/1427 ,  H01L2924/15724 ,  H01L2924/15747 ,  H01L2924/19011 ,  H01L2924/19042 ,  H01L2924/19102 ,  H05K1/0209 ,  H05K1/165 ,  H05K1/181 ,  H05K1/184 ,  H05K1/185 ,  H05K2201/1003 ,  H05K2201/10166 ,  H01L2924/00014

Abstract: A semiconductor package includes a semiconductor die comprising a control transistor and a sync transistor, an integrated output inductor comprising a winding around a core, and coupled to the semiconductor die. The winding comprises a plurality of conductive clips situated above a printed circuit board (PCB) and connected to a plurality of conductive segments in the PCB. The control transistor and the sync transistor are configured as a half-bridge. The integrated output inductor is coupled to a switched node of the half-bridge. At least one of the plurality of conductive clips includes a partially etched portion and a non-etched portion. The semiconductor die is attached to the integrated output inductor by a die attach material. The semiconductor die and the integrated output inductor are encapsulated in a molding compound.